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| 型號： | AM24LC21NA |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DRAM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 該CAT24FC02是一個2 KB的EEPROM的國內(nèi)256個8位每字舉辦的串行CMOS |
| 文件頁數(shù)： | 7/13頁 |
| 文件大?。?/td> | 220K |
| 代理商： | AM24LC21NA |
AM24LC21
(Preliminary)
Dual Mode, 1K-bits (128 x 8) 2-Wire Serial
EEPROM
(B)
(A)
Anachip Corp.
www.anachip.com.tw
Rev 0.0 Aug 10, 2002
7/13
SCL
SDA
(A)
(C)
(D)
(D)
START
Condition
Address or
acknowledge
valid
Data allowed to change
STOP
condition
Figure 3-3. Data transfer sequence on the serial bus
3.1.4 Data Valid (D)
The state of the data line represents valid data
when, after a START condition, the data line is
stable for the duration of the HIGH period of the
clock signal. The data on the line must be changed
during the LOW period of the clock signal. There is
one clock pulse per bit of data. Each data transfer
is initiated with a START condition and terminated
with a STOP condition. The number of the data
bytes transferred between the START and STOP
conditions is determined by the master device and
is theoretically unlimited, although only the last
eight will be stored when doing a write operation.
When an overwrite does occur it will replace data in
a first in first out fashion.
3.1.5 Acknowledge
Each receiving device, when addressed, is obliged
to generate an acknowledge after the reception of
each byte. The master device must generate an
extra clock pulse which is associated with this
acknowledge bit.
Note:
The
AM24LC21
does
acknowledge bits if an internal programming cycle
is in progress.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in
such a way that the SDA line is stable LOW during
the HIGH period of the acknowledge related clock
pulse. Of course, setup and hold times must be
taken into account. A master must signal an end of
data to the slave by not generating an acknowledge
bit on the last byte that has been clocked out of the
slave. In this case, the slave must leave the data
line HIGH to enable the master to generate the
STOP condition.
not
generate
any
SCL
SDA
START
STOP
T
SU:STO
V
HYS
T
HD:STA
T
SU:STA
Figure 3-4. Bus timing start/stop
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| AM24LC21S | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| AM24LC21SA | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM24LC21S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM |
| AM24LC21SA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM |
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