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參數(shù)資料
| 型號(hào)： | AM24LC21NA |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DRAM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 該CAT24FC02是一個(gè)2 KB的EEPROM的國(guó)內(nèi)256個(gè)8位每字舉辦的串行CMOS |
| 文件頁數(shù)： | 11/13頁 |
| 文件大?。?/td> | 220K |
| 代理商： | AM24LC21NA |
AM24LC21
(Preliminary)
Dual Mode, 1K-bits (128 x 8) 2-Wire Serial
EEPROM
Anachip Corp.
www.anachip.com.tw
Rev 0.0 Aug 10, 2002
11/13
S
T
O
P
N
O
A
C
K
S
S
T
A
R
T
Control
Byte
Word
address
Control
Byte
Bus activity
SDA Line
Bus activity
Master
A
C
K
A
C
K
A
C
K
Data(n)
P
S
S
T
A
R
T
Figure 7-2. Random read
S
T
O
P
N
O
A
C
K
Data(n)
Data(n+1)
Data(n+2)
Bus activity
SDA Line
Bus activity
Master
A
C
K
A
C
K
A
C
K
Data(n+X)
P
A
C
K
Contro
Byte
Figure 7-3. Sequential read
Pin Descriptions (Continued)
SDA
This pin is used to transfer addresses and data into
and out of the device, when the device is in the
bi-directional mode. In the transmit-only mode,
which only allows data to be read from the device,
data is also transferred on the SDA pin. This pin is
an open drain terminal, therefore the SDA bus
requires a pull-up resistor to VCC (typical 10k
for
100 Khz, 1k
for 400 Khz).
For normal data transfer in the bi-directional mode,
SDA is allowed to change only during SCL low.
Changes during SCL high are reserved for
indicating the START and STOP conditions.
SCL
This pin is the clock input for the bi-directional
mode, and is used to synchronize data transfer to
and from the device. It is also used as the signaling
input to switch the device from the transmit only
mode to the bi-directional mode. It must remain
high for the chip to continue operation in the
transmit only mode.
VCLK
This pin is the clock input for the transmit only
mode. In the transmit only mode, each bit is
clocked out on the rising edge of this signal. In the
bi-directional mode, a high logic level is required on
this pin to enable write capability.
WP
When using the AM24LC21 in the bi-directional
Mode, the VCLK pin operates as the write protect
control pin. Setting VCLK high allows normal write
operations, while setting VCLK low prevents writing
to any location in the array. Connecting the VCLK
pin to VSS would allow the AM24LC21 to operate
as a serial ROM, although this configuration would
prevent using the device in the transmit-only mode.
If WP is connected to GND, PROGRAM operation
onto the whole memory will not be executed. READ
operation are possible. If WP is connected to Vcc,
normal
memory
operation
READ/WRITE over the entire memory is possible.
is
enabled,
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| AM24LC21S | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| AM24LC21SA | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
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|---|---|
| AM24LC21S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM |
| AM24LC21SA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM |
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