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參數(shù)資料
| 型號： | AK4640 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 16BIT CODEC WITH MIC /HP/SPK-AMPl |
| 中文描述： | 16位編解碼器麥克風(fēng)/惠普/胰腎聯(lián)合移植，AMPl |
| 文件頁數(shù)： | 68/76頁 |
| 文件大?。?/td> | 634K |
| 代理商： | AK4640 |
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ASAHI KASEI
[AK4640]
MS0273-E-00
2004/03
- 68 -
MIC Input Recording
FS2-0 bits
(Addr:05H, D7-5)
MIC Control
(Addr:07H, D2-0)
PMADC bit
(Addr:00H, D0)
PMMIC bit
(Addr:00H, D1)
ADC Internal
State
XXX
000
00001
XX1XX
Power Down
Initialize Normal State Power Down
2081 / fs
(1)
(2)
(6)
(7)
ALC1 State
ALC1 Enable
ALC1 Disable
ALC1 Disable
(5)
ALC1 Control 1
(Addr:08H)
XXH
00H
(3)
ALC1 Control 2
(Addr:0AH)
XXH
47H
(4)
ALC1 Control 3
(Addr:09H)
XXH
61H or 21H
Example :
X’tal and PLL are used.
Sampling Frequency : 8kHz
Mic Select : Internal Mic
Pre Mic AMP : +20dB
MIC Power On
ALC1 setting : Refer to Figure 9
ALC2 bit = “1”(default)
(1) Addr:05H, Data:E0H
(3) Addr:08H, Data:00H
(4) Addr:0AH, Data:47H
(5) Addr:09H, Data:61H
(2) Addr:07H, Data:0DH
(6) Addr:00H, Data 83H
Recording
(7) Addr:00H, Data 80H
Figure 50. MIC Input Recording Sequence
<Example>
This sequence is an example of ALC1 setting in the case that fs=8kHz and ALC1 operation starts from IPGA=0dB.
If the parameter of the ALC1 is changed, please refer to “Figure 20. Registers set-up sequence at ALC1 operation”
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS2-0 bits). When the AK4640 is PLL mode, MIC and ADC should be
powered-up in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up MIC input (Addr: 07H)
(3) Set up Timer Select for ALC1 (Addr: 08H)
(4) Set up REF value for ALC1 (Addr: 0AH)
(5) Set up LMTH, RATT, LMAT1-0, ALC1 bits (Addr: 09H)
(6) Power Up MIC and ADC: PMMIC bit = PMADC bit = “0”
→
“1”
The initialization cycle time of ADC is 2081/fs=47.2ms@fs=44.1kHz.
After the ALC1 bit is set to “1” and MIC block is powered-up, the ALC1 operation starts from IPGA initial
value (0dB).
(7) Power Down MIC and ADC: PMMIC bit = PMADC bit = “1”
→
“0”
When the registers for the ALC1 operation are not changed, ALC1 bit may be keeping “1”. The ALC1
operation is disabled because the MIC block is powered-down. If the registers for the ALC1 operation are also
changed when the sampling frequency is changed, it should be done after the AK4640 goes to the manual
mode (ALC1 bit = “0”) or MIC block is powered-down (PMMIC bit = “0”). IPGA gain is reset when PMMIC
bit is “0”, and then IPGA operation starts from the default value when PMMIC is changed to “1”.
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| AK4643EN | Stereo CODEC with MIC/HP/RCV/SPK-AMP |
| AK4645EZ | Stereo CODEC with MIC/HP-AMP |
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| AK4640_05 | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit ツヒ CODEC with MIC/HP/SPK-AMP |
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| AK4640VN | 制造商:AKM 制造商全稱:AKM 功能描述:16BIT CODEC WITH MIC /HP/SPK-AMPl |
| AK4641 | 制造商:AKM 制造商全稱:AKM 功能描述:16 BIT CODEC WITH BLUETOOTH INTERFACE |
| AK4641EN | 制造商:AKM 制造商全稱:AKM 功能描述:16bit stereo CODEC with built-in Microphone-amplifier and 16bit Mono CODEC for Bluetooth Interface. |
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