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參數(shù)資料
| 型號(hào)： | AK4640 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 16BIT CODEC WITH MIC /HP/SPK-AMPl |
| 中文描述： | 16位編解碼器麥克風(fēng)/惠普/胰腎聯(lián)合移植，AMPl |
| 文件頁(yè)數(shù)： | 56/76頁(yè) |
| 文件大?。?/td> | 634K |
| 代理商： | AK4640 |
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ASAHI KASEI
[AK4640]
MS0273-E-00
2004/03
- 56 -
Addr
09H
Register Name
ALC Mode Control 1
R/W
Default
D7
0
RD
0
D6
ALC2
R/W
1
D5
ALC1
R/W
0
D4
D3
D2
D1
RATT
R/W
0
D0
ZELM
R/W
0
LMAT1
R/W
0
LMAT0
R/W
0
LMTH
R/W
0
LMTH: ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level (see Table 28)
The ALC1 limiter detection level and the ALC1 recovery counter reset level may be offset by about
±
2dB.
Default is “0”.
LMTH
0
1
ALC1 Limiter Detection Level
ADC Input
≥
6.0dBFS
ADC Input
≥
4.0dBFS
Table 28. ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level
ALC1 Recovery Waiting Counter Reset Level
6.0dBFS
>
ADC Input
≥
8.0dBFS
4.0dBFS
>
ADC Input
≥
6.0dBFS
Default
RATT: ALC1 Recovery GAIN Step (see Table 29)
During the ALC1 recovery operation, the number of steps changed from the current IPGA value is set. For
example, when the current IPGA value is 30H and RATT bit = “1” is set, the IPGA changes to 32H by the
ALC1 recovery operation and the output signal level is gained up by 1dB (=0.5dB x 2). When the IPGA value
exceeds the reference level (REF6-0 bits), the IPGA value does not increase.
RATT
0
1
Table 29. ALC1 Recovery Gain Step Setting
GAIN STEP
1
2
Default
LMAT1-0: ALC1 Limiter ATT Step (see Table 30)
During the ALC1 limiter operation, when either Lch or Rch exceeds the ALC1 limiter detection level set by
LMTH, the number of steps attenuated from the current IPGA value is set. For example, when the current
IPGA value is 47H and the LMAT1-0 bits = “11”, the IPGA transition to 43H when the ALC1 limiter
operation starts, resulting in the input signal level being attenuated by 2dB (=0.5dB x 4). When the attenuation
value exceeds IPGA = “00” (
8dB), it clips to “00”.
LMAT1
0
1
1
LMAT0
0
1
0
1
ATT STEP
1
2
3
4
Default
Table 30. ALC1 Limiter ATT Step Setting
ZELM: Enable zero crossing detection at ALC1 Limiter operation
0: Enable (Default)
1: Disable
When the ZELM bit = “0”, the IPGA of each L/R channel perform a zero crossing or timeout independently
and the IPGA value is changed by the ALC1 operation. The zero crossing timeout is the same as the ALC1
recovery operation. When the ZELM bit = “1”, the IPGA value is changed immediately.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4640VG | 16BIT CODEC WITH MIC /HP/SPK-AMPl |
| AK4640VN | 16BIT CODEC WITH MIC /HP/SPK-AMPl |
| AK4642EN | Stereo CODEC with MIC/HP/SPK-AMP |
| AK4643EN | Stereo CODEC with MIC/HP/RCV/SPK-AMP |
| AK4645EZ | Stereo CODEC with MIC/HP-AMP |
相關(guān)代理商/技術(shù)參數(shù) |
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| AK4640_05 | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit ツヒ CODEC with MIC/HP/SPK-AMP |
| AK4640VG | 制造商:AKM 制造商全稱:AKM 功能描述:16BIT CODEC WITH MIC /HP/SPK-AMPl |
| AK4640VN | 制造商:AKM 制造商全稱:AKM 功能描述:16BIT CODEC WITH MIC /HP/SPK-AMPl |
| AK4641 | 制造商:AKM 制造商全稱:AKM 功能描述:16 BIT CODEC WITH BLUETOOTH INTERFACE |
| AK4641EN | 制造商:AKM 制造商全稱:AKM 功能描述:16bit stereo CODEC with built-in Microphone-amplifier and 16bit Mono CODEC for Bluetooth Interface. |
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