參數(shù)資料
型號: AK4640
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: Codec
英文描述: 16BIT CODEC WITH MIC /HP/SPK-AMPl
中文描述: 16位編解碼器麥克風/惠普/胰腎聯(lián)合移植,AMPl
文件頁數(shù): 40/76頁
文件大小: 634K
代理商: AK4640
ASAHI KASEI
[AK4640]
MS0273-E-00
2004/03
- 40 -
ALC2 Operation
Input resistance of the ALC2 (MIN pin) is 24k
(typ) and centered around VCOM voltage. (see Figure 29. 0dBV=1Vrms
=2.828Vpp)
The limiter detection level is proportional to HVDD. The ALC2 circuit limits the output level when the input signal
exceeds –5.2dBV (=FS
1.9dB@HVDD=3.3V). When a continuous signal of –5.2dBV or greater is input to the ALC2
circuit, the change period of the ALC2 limiter operation is set by the ROTM bit and the attenuation level is 0.5dB/step.
The ALC2 recovery operation uses zero crossings and gains of 1dB/step. The ALC2 recovery operation is done until the
input level of the Speaker-amp goes to –7.2dBV(=FS-3.9dB@HVDD=3.3V). The ROTM bit sets the ALC2 recovery
operation period.
When the input signal is between –5.2dBV and –7.2dBV, the ALC2 limiter or recovery operations are not done.
When the PMSPK bit changes from “0” to “1”, the initilization cycle (2048/fs = 46.4ms @fs=44.1kHz at ROTM bit =
“0”, 512/fs = 11.4ms @fs=44.1kHz at the ROTM bit = “1”) starts. The ALC2 is disabled during the initilization cycle and
the ALC2 starts after completing the initilization cycle.
Parameter
ALC2 Limiter operation
Operation Start Level
5.2dBV
ROTM bit = “0”
2/fs = 45
μ
s@fs=44.1kHz
Period
ROTM bit = “1”
2/fs = 181
μ
s@fs=11.025kHz
Zero-crossing Detection
Disabled
ATT/GAIN
0.5dB step
Table 23. Limiter /Recovery of ALC2 at HVDD=3.3V
ALC2 Recovery operation
7.2dBV
2048/fs = 46.4ms@fs=44.1kHz
512/fs = 46.4ms@fs=11.025kHz
Enabled (Timeout = 2048/fs)
1dB step
-15.3dBV
FS
FS-12dB
0dBV
FS-1.9dB = -5.2dBV
1.0dBV
Full-differential
-3.3dBV
-10dBV
-3.0dBV
-5.0dBV
-20dBV
-30dBV
-23.3dBV
-8dB
-15.3dBV
-11.3dBV
-3.3dBV
FS-3.9dB = -7.2dBV
+8.1dB
+16.1dB
+4.1dB
-1.9dB
+8.2dB
-8dB
Single-ended
DATT
DAC
ALC2
SPK-AMP
3.0dBV(250mW@8ohm)
+8.2dB
+2.2dB
+2.2dB
Figure 29. Speaker-amp Output Level Diagram (HVDD=3.3V, DATT=
8.0dB, ALC2= “1”)
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