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參數(shù)資料
| 型號： | AK4640 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 16BIT CODEC WITH MIC /HP/SPK-AMPl |
| 中文描述： | 16位編解碼器麥克風(fēng)/惠普/胰腎聯(lián)合移植，AMPl |
| 文件頁數(shù)： | 27/76頁 |
| 文件大小： | 634K |
| 代理商： | AK4640 |
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ASAHI KASEI
[AK4640]
MS0273-E-00
2004/03
- 27 -
System Reset
Upon power-up, reset the AK4640 by bringing the PDN pin = “L”. This ensures that all internal registers are reset to their
initial values.
The ADC enters an initialization cycle that starts when the PMADC bit is changed from “0” to “1”. The initialization
cycle time is 2081/fs, or 47.2ms@fs=44.1kHz. During the initialization cycle, the ADC digital data outputs of both
channels are forced to a 2's compliment, “0”. The ADC output reflects the analog input signal after the initialization cycle
is complete. The DAC does not require an initialization cycle.
Audio Interface Format
Three types of data formats are available and are selected by setting the DIF1-0 bits (Table 13). In all modes, the serial
data is MSB first, 2’s complement format. The SDTO is clocked out on the falling edge of BICK and the SDTI is latched
on the rising edge. All data formats can be used in both master and slave modes. LRCK and BICK are output from
AK4640 in master mode, but must be input to AK4640 in slave mode. If 16bit data that ADC outputs is converted to 8bit
data by removing LSB 8bit, “
1” at 16bit data is converted to “
1” at 8bit data. And when the DAC playbacks this 8bit
data, “
1” at 8bit data will be converted to “
256” at 16bit data and this is a large offset. This offset can be removed by
adding the offset of “128” to 16bit data before converting to 8bit data.
Mode
DIF1
DIF0
SDTO (ADC)
0
0
0
MSB justified
1
0
1
MSB justified
2
1
0
I
2
S
3
1
1
N/A
Table 13. Audio Interface Format
LRCK
SDTI (DAC)
LSB justified
MSB justified
I
2
S
N/A
BICK
≥
32fs
≥
32fs
≥
32fs
N/A
Figure
Figure 16
Figure 17
Figure 18 Default
-
BICK(32fs)
SDTO(o)
SDTI(i)
0
15 14
15 14
1
10
13
13
2 3
7
7 6 5 4 3 2
1 0
6 5 4 3
1 0
2
9
11 12 13 14 15 0
1 2 3
15 14 13
1
0
15
15
7 6
5 4 3 2
1 0
10
9
11 12 13 14 15
BICK(64fs)
0 1
16
2 3
17 18
31 0
1 2 3
1
0
16 17 18
31
SDTO(o)
SDTI(i)
15 14 13
Don't Care
1 0
1
15
15
2
1 0
15
0
15 14
15
14
Don't Care
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 16. Mode 0 Timing
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