
ASAHI KASEI
[AK4640]
MS0273-E-00
2004/03
- 15 -
DC CHARACTERISTICS
(Ta=
10
~
70
°
C; AVDD, DVDD, PVDD, HVDD=2.4
~
3.6V)
Parameter
High-Level Input Voltage
Low-Level Input Voltage
Input Voltage at AC Coupling
High-Level Output Voltage
Low-Level Output Voltage
(Except SDA pin: Iout=200
μ
A)
(SDA pin: Iout=3mA)
Input Leakage Current
Note 23. The external clock is input to MCKI pin via AC coupled capacitor.
Symbol
VIH
VIL
VAC
VOH
VOL
VOL
Iin
min
typ
-
-
-
-
-
-
-
Max
-
Units
V
V
V
V
(Note 23)
(Iout=
200
μ
A)
70%DVDD
-
50%DVDD
DVDD
0.2
30%DVDD
-
-
-
-
-
0.2
0.4
±
10
V
V
μ
A
SWITCHING CHARACTERISTICS
(Ta=
10
~
70
°
C; AVDD, DVDD, PVDD, HVDD=2.4
~
3.6V; C
L
=20pF)
Parameter
Master Clock Timing
Crystal Resonator
Frequency
External Clock
Frequency
Pulse Width Low
Pulse Width High
AC Pulse Width (Note 24)
MCKO Output
Frequency
Duty Cycle:
except fs=32kHz
fs=32kHz at 256fs (Note 25)
LRCK Timing
Frequency
Duty Cycle
Slave mode
Master mode
Audio Interface Timing
Slave mode
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “
↑
”
(Note 26)
BICK “
↑
” to LRCK Edge
(Note 26)
LRCK to SDTO (MSB) (Except I
2
S mode)
BICK “
↓
” to SDTO
SDTI Hold Time
SDTI Setup Time
Master mode
BICK Frequency
(BF bit = “0”)
(BF bit = “1”)
BICK Duty
BICK “
↓
” to LRCK
BICK “
↓
” to SDTO
SDTI Hold Time
SDTI Setup Time
Note 24. Pulse width to ground level when MCKI is connected to a capacitor in series and a resistor is connected to
ground (Refer to Figure 4).
Note 25. PMPLL bit = “1”.
Note 26. BICK rising edge must not occur at the same time as LRCK edge.
Symbol
min
11.2896
2.048
0.4/fCLK
0.4/fCLK
0.4/fCLK
0.256
40
-
8
45
-
312.5
130
130
50
50
-
-
50
50
-
-
-
80
80
50
50
typ
-
-
-
-
-
-
50
33
-
-
50
-
-
-
-
-
-
-
-
-
64fs
32fs
50
-
-
-
-
max
12.288
12.288
-
-
-
12.288
60
-
48
55
-
-
-
-
-
-
80
80
-
-
-
-
-
80
80
-
-
Units
MHz
MHz
ns
ns
ns
MHz
%
%
kHz
%
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hz
Hz
%
ns
ns
ns
ns
fCLK
tCLKL
tCLKH
tACW
fMCK
dMCK
dMCK
fs
Duty
Duty
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
tSDH
tSDS
fBCK
fBCK
dBCK
tMBLR
tBSD
tSDH
tSDS