參數(shù)資料
型號(hào)： AK4640
廠商： Asahi Kasei Microsystems Co.,Ltd
元件分類： Codec
英文描述： 16BIT CODEC WITH MIC /HP/SPK-AMPl
中文描述： 16位編解碼器麥克風(fēng)/惠普/胰腎聯(lián)合移植，AMPl
文件頁數(shù)： 31/76頁
文件大?。?/td> 634K
代理商： AK4640
ASAHI KASEI
[AK4640]
MS0273-E-00
2004/03
- 31 -
(3) Example of ALC1 Operation
Table 15 shows the examples of the ALC1 setting. In case of this examples, ALC1 operation starts from 0dB.
fs=8kHz
Data
fs=16kHz
Data
fs=44.1kHz
Data
Register Name Comment
Operatio
n
4dBFS
Don’t use
Enable
16ms
Operatio
n
4dBFS
Don’t use
Enable
16ms
Operatio
n
4dBFS
Don’t use
Enable
11.6ms
LMTH
LTM1-0
ZELM
ZTM1-0
Limiter detection Level
Limiter operation period at ZELM = 1
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM1-0 bits should be the same data
as ZTM1-0 bits
Maximum gain at recovery operation
Gain of IPGA before ALC1 operation
start
Limiter ATT Step
Recovery GAIN Step
ALC1 Enable bit
1
00
0
00
1
00
0
01
1
00
0
10
WTM1-0
00
16ms
01
16ms
10
11.6ms
REF6-0
47H
+27.5dB
47H
+27.5dB
47H
+27.5dB
IPGA6-0
10H
0dB
10H
0dB
10H
0dB
LMAT1-0
RATT
ALC1
00
0
1
1 step
1 step
Enable
00
0
1
1 step
1 step
Enable
00
0
1
1 step
1 step
Enable
Table 15. Example of the ALC1 setting
The following registers should not be changed during the ALC1 operation. These bits should be changed after the ALC1
operation is finished by ALC1 bit = “0” or PMMIC bit = “0”.
LTM1-0, LMTH, LMAT1-0, WTM1-0, ZTM1-0, RATT, REF6-0, ZELM bits
IPGA gain at ALC1 operation start can be changed from the default value of IPGA6-0 bits while PMMIC bit is “1” and
ALC1 bit is “0”. When ALC1 bit is changed from “1” to “0”, IPGA holds the last gain value set by ALC1 operation.
Manual Mode
* The value of IPGA should be
the same or smaller than REF’s
WR (ZTM1-0, WTM1-0, LTM1-0)
WR (REF6-0)
WR (IPGA6-0)
ALC1 Operation
Note : WR : Write
WR (ALC1= “1”, LMAT1-0, RATT, LMTH, ZELM)
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 16ms @ fs= 8kHz
Limiter and Recovery Step = 1
Maximum Gain = +27.5dB
Limiter Detection Level = -4dBFS
ALC2 bit = “1” (default)
(1) Addr=08H, Data=00H
(2) Addr=0AH, Data=47H
(4) Addr=09H, Data=61H
(3) Addr=0BH, Data=10H
Figure 20. Registers set-up sequence at ALC1 operation
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