參數(shù)資料
型號： ADZS-BF548-EZLITE
廠商： Analog Devices Inc
文件頁數(shù)： 30/100頁
文件大小： 0K
描述： KIT EZLITE ADZS-BF548
產品培訓模塊： Blackfin® Processor Core Architecture Overview
Blackfin® Device Drivers
Blackfin® Optimizations for Performance and Power Consumption
Blackfin® System Services
特色產品： Blackfin? BF50x Series Processors
標準包裝： 1
系列： Blackfin®
類型： DSP
適用于相關產品： ADSP-BF548
所含物品： 板，軟件，4x4 鍵盤，光學撥輪，QVGA 觸摸屏 LCD 和 40G 硬盤
配用： ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARD
ADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE
相關產品： ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGA
ADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGA
ADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGA
ADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGA
ADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGA
ADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA
ADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA
ADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA
ADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Rev. C
|
Page 35 of 100
|
February 2010
Table 13 and Table 16 describe the voltage/frequency require-
ments for the ADSP-BF54x Blackfin processors’ clocks. Take
care in selecting MSEL, SSEL, and CSEL ratios so as not to
exceed the maximum core clock and system clock. Table 15
describes the phase-locked loop operating conditions.
7 Parameter value applies to pins DQ0–15 and DQS0–1.
8 PB1-0, PE15-14, PG15-11, and PH7-6 are 5.0 V-tolerant (always accept up to 5.5 V maximum V
IH when power is applied to VDDEXT pins). Voltage compliance (on output
VOH) is limited by VDDEXT supply voltage.
9 SDA and SCL are 5.0V tolerant (always accept up to 5.5V maximum V
IH). Voltage compliance on outputs (VOH) is limited by the VDDEXT supply voltage.
10Parameter value applies to USB_DP, USB_DM, and USB_VBUS pins. See Absolute Maximum Ratings on Page 40.
11Parameter value applies to all input and bidirectional pins, except PB1-0, PE15-14, PG15–11, and PH7-6.
12Parameter value applies to pins PG15–11 and PH7-6.
13Parameter value applies to pins PB1-0 and PE15-14. Consult the I2C specification version 2.1 for the proper resistor value and other open drain pin electrical parameters.
14TJ must be in the range: 0°C < TJ < 55°C during OTP memory programming operations.
Table 13. Core Clock Requirements—533 MHz and 600 MHz Speed Grade1
Parameter
Condition
Internal Regulator Setting2
Max
Unit
fCCLK
Core Clock Frequency
VDDINT = 1.30 V minimum
600
MHz
fCCLK
Core Clock Frequency
VDDINT = 1.20 V minimum
1.25 V
533
MHz
fCCLK
Core Clock Frequency
VDDINT = 1.14 V minimum
1.20 V
500
MHz
fCCLK
Core Clock Frequency
VDDINT = 1.045 V minimum
1.10 V
444
MHz
fCCLK
Core Clock Frequency
VDDINT = 0.95 V minimum
1.00 V
400
MHz
fCCLK
Core Clock Frequency
VDDINT = 0.90 Vminimum
0.95 V
333
MHz
2 Use of an internal voltage regulator is not supported on automotive grade and 600 MHz speed grade models
Table 14. Core Clock Requirements—400 MHz Speed Grade1
Parameter
Condition
Internal Regulator Setting2
Max
Unit
fCCLK
Core Clock Frequency
VDDINT = 1.14 V minimum
1.20 V
400
MHz
fCCLK
Core Clock Frequency
VDDINT = 1.045 V minimum
1.10 V
364
MHz
fCCLK
Core Clock Frequency
VDDINT = 0.95 V minimum
1.00 V
333
MHz
fCCLK
Core Clock Frequency
VDDINT = 0.90 V minimum
0.95 V
300
MHz
2 Use of an internal voltage regulator is not supported on automotive grade models
Table 15. Phase-Locked Loop Operating Conditions
Parameter
Min
Max
Unit
fVCO
Voltage Controlled Oscillator (VCO) Frequency
50
Maximum fCCLK
MHz
Table 16. System Clock Requirements
Parameter
Condition
DDR SDRAM Models
Mobile DDR SDRAM Models
Unit
Max
Min
Max
fSCLK
VDDINT ≥ 1.14 V
1
1332
1203
1332
MHz
fSCLK
VDDINT < 1.14 V
100
N/A4
N/A4
MHz
1 f
SCLK must be less than or equal to fCCLK.
2 Rounded number. Actual test specification is SCLK period of 7.5 ns. See Table 26 on Page 43.
3 Rounded number. Actual test specification is SCLK period of 8.33 ns.
4 VDDINT must be greater than or equal to 1.14 V for mobile DDR SDRAM models. See Operating Conditions on Page 34.
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相關代理商/技術參數(shù)
參數(shù)描述
ADZS-BF548-EZLITE 制造商:Analog Devices 功能描述:Evaluation Kit
ADZS-BF548-MPSKIT 功能描述:KIT STARTER MULTIMEDIA BF548 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:Blackfin® 標準包裝:1 系列:PICDEM™ 類型:MCU 適用于相關產品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，線纜，元件，CD，PICkit 編程器 產品目錄頁面:659 (CN2011-ZH PDF)
ADZS-BF549-EZLITE 功能描述:KIT EZLITE ADZS-BF549 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:Blackfin® 標準包裝:1 系列:PICDEM™ 類型:MCU 適用于相關產品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，線纜，元件，CD，PICkit 編程器 產品目錄頁面:659 (CN2011-ZH PDF)
ADZS-BF561-EZLITE 功能描述:BOARD EVAL ADSP-BF561 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:Blackfin® 產品培訓模塊:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色產品:Blackfin? BF50x Series Processors 標準包裝:1 系列:Blackfin® 類型:DSP 適用于相關產品:ADSP-BF548 所含物品:板，軟件，4x4 鍵盤，光學撥輪，QVGA 觸摸屏 LCD 和 40G 硬盤 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相關產品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA
ADZS-BF561-MMSKIT 功能描述:KIT STARTER MULTIMEDIA BF561 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:Blackfin® 標準包裝:1 系列:PICDEM™ 類型:MCU 適用于相關產品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，線纜，元件，CD，PICkit 編程器 產品目錄頁面:659 (CN2011-ZH PDF)
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