- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄11199 > ADUC845BSZ8-5-RL (Analog Devices Inc)IC FLASH MCU W/24BIT ADC 56-CSP PDF資料下載
參數(shù)資料
| 型號(hào)： | ADUC845BSZ8-5-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 89/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FLASH MCU W/24BIT ADC 56-CSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲(chǔ)器容量： | 8KB（8K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.75 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 10x24b; D/A 1x12b，2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ADUC845BSZ8-5-RLDKR |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁當(dāng)前第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁
Data Sheet
ADuC845/ADuC847/ADuC848
Rev. C | Page 81 of 108
Mode 0 (8-Bit Shift Register Mode)
Mode 0 is selected by clearing both the SM0 and SM1 bits in
the SFR SCON. Serial data enters and exits through RxD. TxD
outputs the shift clock. Eight data bits are transmitted or
received. Transmission is initiated by any instruction that writes
to SBUF. The data is shifted out of the RxD line. The 8 bits are
transmitted with the least significant bit (LSB) first.
Reception is initiated when the receive enable bit (REN) is 1
and the receive interrupt bit (RI) is 0. When RI is cleared, the
data is clocked into the RxD line, and the clock pulses are
output from the TxD line as shown in Figure 58.
RxD
(DATA OUT)
TxD
(SHIFT CLOCK)
DATA BIT 0
DATA BIT 1
DATA BIT 6
DATA BIT 7
04741-055
Figure 58. 8-Bit Shift Register Mode
Mode 1 (8-Bit UART, Variable Baud Rate)
Mode 1 is selected by clearing SM0 and setting SM1. Each data
byte (LSB first) is preceded by a start bit (0) and followed by a
stop bit (1). Therefore, 10 bits are transmitted on TxD or are
received on RxD. The baud rate is set by the Timer 1 or Timer 2
overflow rate, or a combination of the two (one for transmission
and the other for reception).
Transmission is initiated by writing to SBUF. The write to SBUF
signal also loads a 1 (stop bit) into the 9th bit position of the
transmit shift register. The data is output bit-by-bit until the
stop bit appears on TxD and the transmit interrupt flag (TI) is
automatically set as shown in Figure 59.
TxD
TI
(SCON.1)
START
BIT
D0
D1
D2
D3
D4
D5
D6
D7
STOP BIT
SET INTERRUPT
I.E., READY FOR MORE DATA
04741-056
Figure 59. 8-Bit Variable Baud Rate
Reception is initiated when a 1-to-0 transition is detected on
RxD. Assuming that a valid start bit is detected, character
reception continues. The start bit is skipped and the 8 data bits
are clocked into the serial port shift register. When all 8 bits
have been clocked in, the following events occur:
The 8 bits in the receive shift register are latched into SBUF.
The 9th bit (stop bit) is clocked into RB8 in SCON.
The receiver interrupt flag (RI) is set.
All of the following conditions must be met at the time the final
shift pulse is generated:
RI = 0
Either SM2 = 0 or SM2 = 1
Received stop bit = 1
If any of these conditions is not met, the received frame is
irretrievably lost, and RI is not set.
Mode 2 (9-Bit UART with Fixed Baud Rate)
Mode 2 is selected by setting SM0 and clearing SM1. In this
mode, the UART operates in 9-bit mode with a fixed baud rate.
The baud rate is fixed at Core_Clk/64 by default, although by
setting the SMOD bit in PCON, the frequency can be doubled
to Core_Clk/32. Eleven bits are transmitted or received: a start
bit (0), 8 data bits, a programmable 9th bit, and a stop bit (1).
The 9th bit is most often used as a parity bit, although it can be
used for anything, including a ninth data bit if required.
To transmit, the 8 data bits must be written into SBUF. The
ninth bit must be written to TB8 in SCON. When transmission
is initiated, the 8 data bits (from SBUF) are loaded into the
transmit shift register (LSB first). The contents of TB8 are
loaded into the 9th bit position of the transmit shift register.
The transmission starts at the next valid baud rate clock. The
TI flag is set as soon as the stop bit appears on TxD.
Reception for Mode 2 is similar to that of Mode 1. The 8 data
bytes are input at RxD (LSB first) and loaded onto the receive
shift register. When all 8 bits have been clocked in, the
following events occur:
The 8 bits in the receive shift register are latched into SBUF.
The 9th data bit is latched into RB8 in SCON.
The receiver interrupt flag (RI) is set.
All of the following conditions must be met at the time the final
shift pulse is generated:
RI = 0
Either SM2 = 0 or SM2 = 1
Received stop bit = 1
If any of these conditions is not met, the received frame is
irretrievably lost, and RI is not set.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC74HCT4051ADG | ANALOG MULTIPLEXERS/DEMU SOIC16 |
| ADUC7036DCPZ | IC MCU 96K FLASH DUAL 48LFCSP |
| MC74HC4051ADTR2G | IC MUX/DEMUX 8X1 16TSSOP |
| ADUC7036BCPZ | IC MCU FLASH 96K ANLGI/O 48LFCSP |
| ATSAM3X4EA-AU | IC MCU 2X128KB CORTEX-M3 144-QFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADUC846 | 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter, Dual 16-Bit ADCs with Embedded 62kB FLASH MCU |
| ADUC846BCP32-3 | 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter, Dual 16-Bit ADCs with Embedded 62kB FLASH MCU |
| ADUC846BCP32-5 | 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter, Dual 16-Bit ADCs with Embedded 62kB FLASH MCU |
| ADUC846BCP62-3 | 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter, Dual 16-Bit ADCs with Embedded 62kB FLASH MCU |
| ADUC846BCP62-5 | 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter, Dual 16-Bit ADCs with Embedded 62kB FLASH MCU |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。