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參數(shù)資料
| 型號(hào)： | ADUC845BSZ8-5-RL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 60/108頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FLASH MCU W/24BIT ADC 56-CSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲(chǔ)器容量： | 8KB（8K x 8） |
| 程序存儲(chǔ)器類(lèi)型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.75 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 10x24b; D/A 1x12b，2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱(chēng)： | ADUC845BSZ8-5-RLDKR |
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Data Sheet
ADuC845/ADuC847/ADuC848
Rev. C | Page 55 of 108
SOURCE/SINK CURRENT (mA)
3
0
5
10
15
OUTPUT
VOLTAGE
(V)
2
1
0
DAC LOADED WITH 0000H
DAC LOADED WITH 0FFFH
04741-036
Figure 36. Source and Sink Current Capability with VREF = AVDD = 3 V
For larger loads, the current drive capability may not be suffi-
cient. To increase the source and sink current capability of the
DAC, an external buffer should be added as shown in Figure 37.
ADuC845/
ADuC847/
ADuC848
DAC
04741-037
14
Figure 37. Buffering the DAC Output
The internal DAC output buffer also features a high impedance
disable function. In the chip’s default power-on state, the DAC
is disabled and its output is in a high impedance state (or three-
state) where it remains inactive until enabled in software. This
means that if a zero output is desired during power-on or
power-down transient conditions, a pull-down resistor must be
added to each DAC output. Assuming that this resistor is in
place, the DAC output remains at ground potential whenever
the DAC is disabled.
PULSE-WIDTH MODULATOR (PWM)
The ADuC845/ADuC847/ADuC848 has a highly flexible PWM
offering programmable resolution and an input clock. The
PWM can be configured in six different modes of operation.
Two of these modes allow the PWM to be configured as a Σ-
Δ
DAC with up to 16 bits of resolution. A block diagram of the
PWM is shown in Figure 38.
CLOCK
SELECT
PROGRAMMABLE
DIVIDER
COMPARE
MODE
PWM0H/L
PWM1H/L
12.583MHz (FVCO)
32.768kHz/15
32.768kHz (FXTAL)
EXTERNAL CLOCK ON P2.7
P2.5
P2.6
16-BIT PWM COUNTER
04741-
038
Figure 38. PWM Block Diagram
The PWM uses control SFR, PWMCON, and four data SFRs:
PWM0H, PWM0L, PWM1H, and PWM1L.
PWMCON (as described in Table 34) controls the different
modes of operation of the PWM as well as the PWM clock
frequency. PWM0H/L and PWM1H/L are the data registers that
determine the duty cycles of the PWM outputs at P2.5 and P2.6.
To use the PWM user software, first write to PWMCON to
select the PWM mode of operation and the PWM input clock.
Writing to PWMCON also resets the PWM counter. In any of
the 16-bit modes of operation (Modes 1, 3, 4, 6), user software
should write to the PWM0L or PWM1L SFRs first. This value is
written to a hidden SFR. Writing to the PWM0H or PWM1H
SFRs updates both the PWMxH and the PWMxL SFRs but does
not change the outputs until the end of the PWM cycle in
progress. The values written to these 16-bit registers are then
used in the next PWM cycle.
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