參數(shù)資料
型號(hào)： ADUC845BSZ8-5-RL
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 63/108頁(yè)
文件大?。?/td> 0K
描述： IC FLASH MCU W/24BIT ADC 56-CSP
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 12.58MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PSM，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類(lèi)型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 4.75 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x24b; D/A 1x12b，2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 52-QFP
包裝： 標(biāo)準(zhǔn)包裝
其它名稱(chēng)： ADUC845BSZ8-5-RLDKR
ADuC845/ADuC847/ADuC848
Data Sheet
Rev. C | Page 58 of 108
Mode 3 (Twin 16-Bit PWM)
In Mode 3, the PWM counter is fixed to count from 0 to 65536,
giving a fixed 16-bit PWM. Operating from the 12.58 MHz core
clock results in a PWM output rate of 192 Hz. The duty cycle of
the PWM outputs at P2.5 and P2.6 are independently
programmable.
As shown in Figure 41, while the PWM counter is less than
PWM0H/L, the output of PWM0 (P2.5) is high. Once the
PWM counter equals PWM0H/L, PWM0 (P2.5) goes low and
remains low until the PWM counter rolls over.
Similarly, while the PWM counter is less than PWM1H/L, the
output of PWM1 (P2.6) is high. Once the PWM counter equals
PWM1H/L, PWM1 (P2.6) goes low and remains low until the
PWM counter rolls over.
In this mode, both PWM outputs are synchronized, that is, once
the PWM counter rolls over to 0, both PWM0 (P2.5) and PWM1
(P2.6) go high.
P2.6
P2.5
PWM COUNTER
PWM1H/L
0
65536
PWM0H/L
04741-041
Figure 41. PWM Mode 3
Mode 4 (Dual NRZ 16-Bit Σ- DAC)
Mode 4 provides a high speed PWM output similar to that of a
Σ-Δ DAC. Typically, this mode is used with the PWM clock
equal to 12.58 MHz.
In this mode, P2.5 and P2.6 are updated every PWM clock
(80 ns in the case of 12.58 MHz). Over any 65536 cycles (16-bit
PWM), PWM0 (P2.5) is high for PWM0H/L cycles and low for
(65536 – PWM0H/L) cycles. Similarly, PWM1 (P2.6) is high for
PWM1H/L cycles and low for (65536 – PWM1H/L) cycles.
If PWM1H is set to 4010H (slightly above one-quarter of FS),
typically P2.6 is low for three clocks and high for one clock
(each clock is approximately 80 ns). Over every 65536 clocks,
the PWM compromises for the fact that the output should be
slightly above one-quarter of full scale, by having a high cycle
followed by only two low cycles.
12.583MHz
16-BIT
80
s
0
16-BIT
CARRY OUT AT P2.5
CARRY OUT AT P2.6
PWM0H/L = C000H
PWM1H/L = 4000H
0
1
0
LATCH
0
1
0
04741-042
80
s
Figure 42. PWM Mode 4
For faster DAC outputs (at lower resolution), write 0s to the
LSBs that are not required with a 1 in the LSB position. If, for
example, only 12-bit performance is required, write 0001 to the
4 LSBs. This means that a 12-bit accurate Σ-Δ DAC output can
occur at 3 kHz. Similarly, writing 00000001 to the 8 LSBs gives
an 8-bit accurate Σ-Δ DAC output at 49 kHz.
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