參數(shù)資料
型號(hào)： ADUC845BSZ8-5-RL
廠商： Analog Devices Inc
文件頁數(shù)： 31/108頁
文件大?。?/td> 0K
描述： IC FLASH MCU W/24BIT ADC 56-CSP
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 12.58MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PSM，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大小： 4K x 8
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 4.75 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x24b; D/A 1x12b，2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 52-QFP
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： ADUC845BSZ8-5-RLDKR
Data Sheet
ADuC845/ADuC847/ADuC848
Rev. C | Page 29 of 108
ADC Noise Performance with Chop Enabled (CHOP = 0)
noise and output peak-to-peak resolution in bits (rounded to
the nearest 0.5 LSB) for some typical output update rates for the
ADuC845, ADuC847, and ADuC848. The numbers are typical
and are generated at a differential input voltage of 0 V and a
common-mode voltage of 2.5 V. The output update rate is
selected via the SF7 to SF0 bits in the SF filter register. It is
important to note that the peak-to-peak resolution figures
represent the resolution for which there is no code flicker
within a 6-sigma limit.
The output noise comes from two sources. The first source is
the electrical noise in the semiconductor devices (device noise)
used in the implementation of the modulator. The second
source is quantization noise, which is added when the analog
input is converted to the digital domain. The device noise is at a
low level and is independent of frequency. The quantization
noise starts at an even lower level but rises rapidly with increasing
frequency to become the dominant noise source.
The numbers in the tables are given for the bipolar input ranges.
For the unipolar ranges, the rms noise numbers are in the same
range as the bipolar figures, but the peak-to-peak resolution is
based on half the signal range, which effectively means losing
1 bit of resolution.
Table 10. ADuC845 and ADuC847 Typical Output RMS Noise (V) vs. Input Range and Update Rate with Chop Enabled
Input Range
SF Word
Data Update Rate (Hz)
±20 mV
±40 mV
±80 mV
±160 mV
±320 mV
±640 mV
±1.28 V
±2.56 V
13
105.03
1.75
1.30
1.65
1.5
2.1
3.1
7.15
13.3
23
59.36
1.25
0.95
1.08
0.94
1.0
1.87
3.24
7.1
27
50.56
1.0
0.85
1.13
1.56
2.9
3.6
69
19.79
0.63
0.68
0.52
0.7
0.61
1.1
1.3
2.75
255
5.35
0.31
0.38
0.34
0.32
0.4
0.45
0.68
1.22
Table 11. ADuC845 and ADuC847 Typical Peak-to-Peak Resolution (Bits) vs. Input Range and Update Rate with Chop Enabled
Input Range
SF Word
Data Update Rate (Hz)
±20 mV
±40 mV
±80 mV
±160 mV
±320 mV
±640 mV
±1.28 V
±2.56 V
13
105.03
12
13
14
15
15.5
16
23
59.36
12
13.5
14.5
15.5
16.5
17
16.5
27
50.56
12.5
13.5
15
16
16.5
17
17.5
69
19.79
13
14
15.5
16
17.5
18
255
5.35
14.5
15
16
17
18
18.5
19
19.5
Table 12. ADuC848 Typical Output Noise (V) vs. Input Range and Update Rate with Chop Enabled
Input Range
SF Word
Data Update Rate (Hz)
±20 mV
±40 mV
±80 mV
±160 mV
±320 mV
±640 mV
±1.28 V
±2.56 V
13
105.03
1.75
1.30
1.65
1.5
2.1
3.1
7.15
13.3
23
59.36
1.25
0.95
1.08
0.94
1.0
1.87
3.24
7.1
27
50.56
1.0
0.85
1.13
1.56
2.9
3.6
69
19.79
0.63
0.68
0.52
0.7
0.61
1.1
1.3
2.75
255
5.35
0.31
0.38
0.34
0.32
0.4
0.45
0.68
1.22
Table 13. ADuC848 Typical Peak-to-Peak Resolution (Bits) vs. Input Range and Update Rate with Chop Enabled
Input Range
SF Word
Data Update Rate (Hz)
±20 mV
±40 mV
±80 mV
±160 mV
±320 mV
±640 mV
±1.28 V
±2.56 V
13
105.03
12
13
14
15
15.5
16
23
59.36
12
13.5
14.5
15.5
16
17
16
27
50.56
12.5
13.5
15
16
69
19.79
13
14
15.5
16
255
5.35
14.5
15
16
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