參數(shù)資料
型號(hào)： ADUC845BSZ8-5-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 58/108頁(yè)
文件大小： 0K
描述： IC FLASH MCU W/24BIT ADC 56-CSP
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 12.58MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PSM，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大小： 4K x 8
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 4.75 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x24b; D/A 1x12b，2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 52-QFP
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： ADUC845BSZ8-5-RLDKR
Data Sheet
ADuC845/ADuC847/ADuC848
Rev. C | Page 53 of 108
DAC CIRCUIT INFORMATION
The ADuC845/ADuC847/ADuC848 incorporate a 12-bit,
voltage output DAC on-chip. It has a rail-to-rail voltage output
buffer capable of driving 10 k/100 pF, and has two selectable
ranges, 0 V to VREF and 0 V to AVDD. It can operate in 12-bit or
8-bit mode. The DAC has a control register, DACCON, and two
data registers, DACH/L. The DAC output can be programmed
to appear at Pin 14 (DAC) or Pin 13 (AINCOM).
In 12-bit mode, the DAC voltage output is updated as soon as
the DACL data SFR is written; therefore, the DAC data registers
should be updated as DACH first, followed by DACL. The 12-
bit DAC data should be written into DACH/L right-justified
such that DACL contains the lower 8 bits, and the lower nibble
of DACH contains the upper 4 bits.
DACCON Control Register
SFR Address:
FDH
Power-On Default:
00H
Bit Addressable:
No
Table 33. DACCON—DAC Configuration Commands
Bit No.
Name
Description
7
–––
Not Implemented. Write Don’t Care.
6
–––
Not Implemented. Write Don’t Care.
5
–––
Not Implemented. Write Don’t Care.
4
DACPIN
DAC Output Pin Select.
Set to 1 by the user to direct the DAC output to Pin 13 (AINCOM).
Cleared to 0 by the user to direct the DAC output to Pin 14 (DAC).
3
DAC8
DAC 8-Bit Mode Bit.
Set to 1 by the user to enable 8-bit DAC operation. In this mode, the 8 bits in DACL SFR are routed to the 8 MSBs
of the DAC, and the 4 LSBs of the DAC are set to 0.
Cleared to 0 by the user to enable 12-bit DAC operation. In this mode, the 8 LSBs of the result are routed to
DACL, and the upper 4 MSB bits are routed to the lower 4 bits of DACH.
2
DACRN
DAC Output Range Bit.
Set to 1 by the user to configure the DAC range of 0 V to AVDD.
Cleared to 0 by the user to configure the DAC range of 0 V to 2.5 V (VREF).
1
DACCLR
DAC Clear Bit.
Set to 1 by the user to enable normal DAC operation.
Cleared to 0 by the user to reset the DAC data registers DACL/H to 0.
0
DACEN
DAC Enable Bit.
Set to 1 by the user to enable normal DAC operation.
Cleared to 0 by the user to power down the DAC.
DACH/DACL Data Registers
These DAC data registers are written to by the user to update
the DAC output.
SFR Address:
DACL (DAC data low byte)—FBH
DACH (DAC data high byte)—FCH
Power-On Default:
00H (both registers)
Bit Addressable:
No (both registers)
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