參數(shù)資料
型號： ADUC7060BSTZ32-RL
廠商： Analog Devices Inc
文件頁數(shù)： 83/108頁
文件大小： 0K
描述： IC ARM7 MCU FLASH 32K 48LQFP
產(chǎn)品變化通告： ADuC7060/1 Idd Specification Change 01/Feb/2010
設(shè)計資源： 4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145)
Low power, Long Range, ISM Wireless Measuring Node (CN0164)
標(biāo)準(zhǔn)包裝： 2,000
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 10MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 14
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
RAM 容量： 1K x 32
電壓 - 電源 (Vcc/Vdd)： 2.375 V ~ 2.625 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 5x24b，8x24b，D/A 1x14b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 48-LQFP
包裝： 帶卷 (TR)
ADuC7060/ADuC7061
Data Sheet
Rev. D | Page 76 of 108
Table 85. PWMCON MMR Bit Designations
Bit
Name
Description
15
Reserved
This bit is reserved. Do not write to this bit.
14
Sync
Enables PWM synchronization.
Set to 1 by user so that all PWM counters are reset on the next clock edge after the detection of a high-to-low
transition on the P1.2/SYNC pin.
Cleared by user to ignore transitions on the P1.2/SYNC pin.
13
PWM5INV
Set to 1 by user to invert PWM5.
Cleared by user to use PWM5 in normal mode.
12
PWM3INV
Set to 1 by user to invert PWM3.
Cleared by user to use PWM3 in normal mode.
11
PWM1INV
Set to 1 by user to invert PWM1.
Cleared by user to use PWM1 in normal mode.
10
PWMTRIP
Set to 1 by user to enable PWM trip interrupt. When the PWM trip input (Pin P1.3/TRIP) is low, the PWMEN bit is
cleared and an interrupt is generated.
Cleared by user to disable the PWMTRIP interrupt.
9
ENA
If HOFF = 0 and HMODE = 1. Note that, if not in H-bridge mode, this bit has no effect.
Set to 1 by user to enable PWM outputs.
Cleared by user to disable PWM outputs.
If HOFF = 1 and HMODE = 1, see Table 86.
8:6
PWMCP[2:0]
PWM clock prescaler bits. Sets the UCLK divider.
[000] = UCLK/2.
[001] = UCLK/4.
[010] = UCLK/8.
[011] = UCLK/16.
[100] = UCLK/32.
[101] = UCLK/64.
[110] = UCLK/128.
[111] = UCLK/256.
5
POINV
Set to 1 by user to invert all PWM outputs.
Cleared by user to use PWM outputs as normal.
4
HOFF
High side off.
Set to 1 by user to force PWM0 and PWM2 outputs high. This also forces PWM1 and PWM3 low.
Cleared by user to use the PWM outputs as normal.
3
LCOMP
Load compare registers.
Set to 1 by user to load the internal compare registers with the values in PWMxCOMx on the next transition of the
PWM timer from 0x00 to 0x01.
Cleared by user to use the values previously stored in the internal compare registers.
2
DIR
Direction control.
Set to 1 by user to enable PWM0 and PWM1 as the output signals while PWM2 and PWM3 are held low.
Cleared by user to enable PWM2 and PWM3 as the output signals while PWM0 and PWM1 are held low.
1
HMODE
Enables H-bridge mode.1
Set to 1 by user to enable H-bridge mode and Bit 1 to Bit 5 of PWMCON.
Cleared by user to operate the PWMs in standard mode.
0
PWMEN
Set to 1 by user to enable all PWM outputs.
Cleared by user to disable all PWM outputs.
1 In H-bridge mode, HMODE = 1. See Table 86 to determine the PWM outputs.
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