參數(shù)資料
型號: ADUC7060BSTZ32-RL
廠商: Analog Devices Inc
文件頁數(shù): 74/108頁
文件大?。?/td> 0K
描述: IC ARM7 MCU FLASH 32K 48LQFP
產(chǎn)品變化通告: ADuC7060/1 Idd Specification Change 01/Feb/2010
設(shè)計資源: 4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145)
Low power, Long Range, ISM Wireless Measuring Node (CN0164)
標準包裝: 2,000
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 10MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 14
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
RAM 容量: 1K x 32
電壓 - 電源 (Vcc/Vdd): 2.375 V ~ 2.625 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 5x24b,8x24b,D/A 1x14b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 48-LQFP
包裝: 帶卷 (TR)
ADuC7060/ADuC7061
Data Sheet
Rev. D | Page 68 of 108
Timer0 Capture Register
Name:
T0CAP
Address:
0xFFFF0330
Default value:
0x00000000
Access:
Read only
Function:
This 32-bit register holds the 32-bit value captured by an enabled IRQ event.
Timer0 Control Register
Name:
T0CON
Address:
0xFFFF0328
Default value:
0x01000000
Access:
Read and write
Function:
This 32-bit MMR configures the mode of operation of Timer0.
Table 80. T0CON MMR Bit Designations
Bit
Name
Description
31:24
T0PVAL
8-bit postscaler.
By writing to these eight bits, a value is written to the postscaler. Writing 0 is interpreted as a 1.
By reading these eight bits, the current value of the counter is read.
23
T0PEN
Timer0 enable postscaler.
Set to enable the Timer0 postscaler. If enabled, interrupts are generated after T0CON[31:24] periods
as defined by T0LD.
Cleared to disable the Timer0 postscaler.
22:20
Reserved. These bits are reserved and should be written as 0 by user code.
19
T0PCF
Postscaler compare flag; read only. Set if the number of Timer0 overflows is equal to the number written
to the postscaler.
18
T0SRCI
Timer0 interrupt source.
Set to select interrupt generation from the postscaler counter.
Cleared to select interrupt generation directly from Timer0.
17
T0CAPEN
Event enable bit.
Set by user to enable time capture of an event.
Cleared by user to disable time capture of an event.
16:12
T0CAPSEL
Event Select Bits[17:0]. The events are described in Table 78.
11
Reserved bit.
10:9
T0CLKSEL
Clock select.
[00] = 32.768 kHz.
[01] = 10.24 MHz/CD.
[10] = 10.24 MHz.
[11] = P1.0.
8
Count up.
Set by user for Timer0 to count up.
Cleared by user for Timer0 to count down (default).
7
T0EN
Timer0 enable bit.
Set by user to enable Timer0.
Cleared by user to disable Timer0 (default).
6
T0MOD
Timer0 mode.
Set by user to operate in periodic mode.
Cleared by user to operate in free running mode (default).
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