參數(shù)資料
型號(hào)： ADUC7060BSTZ32-RL
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 38/108頁(yè)
文件大?。?/td> 0K
描述： IC ARM7 MCU FLASH 32K 48LQFP
產(chǎn)品變化通告： ADuC7060/1 Idd Specification Change 01/Feb/2010
設(shè)計(jì)資源： 4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145)
Low power, Long Range, ISM Wireless Measuring Node (CN0164)
標(biāo)準(zhǔn)包裝： 2,000
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 10MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 14
程序存儲(chǔ)器容量： 32KB（16K x 16）
程序存儲(chǔ)器類(lèi)型： 閃存
RAM 容量： 1K x 32
電壓 - 電源 (Vcc/Vdd)： 2.375 V ~ 2.625 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 5x24b，8x24b，D/A 1x14b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 48-LQFP
包裝： 帶卷 (TR)
Data Sheet
ADuC7060/ADuC7061
Rev. D | Page 35 of 108
By writing to POWCON1, it is possible to further reduce power
consumption in active mode by powering down the UART, PWM
or I2C/SPI blocks. To access POWCON1, POWKEY3 must be set to
0x76 in the instruction immediately before accessing POWCON1
and POWKEY4 must be set to 0xB1 in the instruction immediately
after.
For example, the following code enables the SPI/I2C blocks but,
powers down the PWM and UART blocks.
POWKEY3 =0x76;
POWCON1 =0x4;
//0x100 PWM; 0x20
Uart; 0x4 SPI/I2C
POWKEY4 =0xB1;
Power and Clock Control Registers
POWKEY1 Register
Name:
POWKEY1
Address:
0xFFFF0404
Default value:
0xXXXX
Access:
Write
Function:
When writing to POWCON0, the value of 0x01
must be written to this register in the instruction
immediately before writing to POWCON0.
POWCON0 Register
Name:
POWCON0
Address:
0xFFFF0408
Default value:
0x7B
Access:
Read and write
Function:
This register controls the clock divide bits
controlling the CPU clock (HCLK).
Table 31. POWCON0 MMR Bit Designations
Bit
Name
Description
7
Reserved
This bit must always be set to 0.
6
XPD
XTAL power-down.
Cleared by user to power down the external crystal circuitry.
Set by user to enable the external crystal circuitry.
5
PLLPD
PLL power-down. Timer peripherals power down if driven from the PLL output clock. Timers driven from an active clock
source remain in normal power mode.
This bit is cleared to 0 to power down the PLL. The PLL cannot be powered down if either the core or peripherals are
enabled; Bit 3, Bit 4, and Bit 5 must be cleared simultaneously.
Set by default, and set by hardware on a wake-up event.
4
PPD
Peripherals power-down. The peripherals that are powered down by this bit are as follows:
SRAM, Flash/EE memory and GPIO interfaces, and SPI/I2C and UART serial ports.
Cleared to power down the peripherals. The peripherals cannot be powered down if the core is enabled; Bit 3 and Bit 4
must be cleared simultaneously.
Set by default and/or by hardware on a wake-up event. Wake-up timer (Timer1) can remain active.
3
COREPD
Core power-down. If user code powers down the MCU, include a dummy MCU cycle after the power-down command is
written to POWCON0.
Cleared to power down the ARM core.
Set by default and set by hardware on a wake-up event.
2:0
CD[2:0]
Core clock depends on CD setting:
[000] = 10.24 MHz
[001] = 5.12 MHz
[010] = 2.56 MHz
[011] = 1.28 MHz [default value]
[100] = 640 kHz
[101] = 320 kHz
[110] = 160 kHz
[111] = 80 kHz
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