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參數(shù)資料
| 型號： | ADUC7060BSTZ32-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 67/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ARM7 MCU FLASH 32K 48LQFP |
| 產(chǎn)品變化通告： | ADuC7060/1 Idd Specification Change 01/Feb/2010 |
| 設(shè)計資源： | 4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145) Low power, Long Range, ISM Wireless Measuring Node (CN0164) |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 10MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 14 |
| 程序存儲器容量： | 32KB（16K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.375 V ~ 2.625 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 5x24b，8x24b，D/A 1x14b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 48-LQFP |
| 包裝： | 帶卷 (TR) |
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Data Sheet
ADuC7060/ADuC7061
Rev. D | Page 61 of 108
FIQSTA Register
Name:
FIQSTA
Address:
0xFFFF0100
Default value: 0x00000000
Access:
Read only
PROGRAMMED INTERRUPTS
Because the programmed interrupts are not maskable, they are
controlled by another register (SWICFG) that writes into both
IRQSTA and IRQSIG registers and/or the FIQSTA and FIQSIG
registers at the same time.
SWICFG
SWICFG is a 32-bit register dedicated to software interrupt,
described in Table 66. This MMR allows control of a pro-
grammed source interrupt.
SWICFG Register
Name:
SWICFG
Address:
0xFFFF0010
Default value: 0x00000000
Access:
Write only
Table 66. SWICFG MMR Bit Designations
Bit
Description
31:3
Reserved.
2
Programmed interrupt FIQ. Setting/clearing this bit
corresponds to setting/clearing Bit 1 of FIQSTA and
FIQSIG.
1
Programmed interrupt IRQ. Setting/clearing this bit
corresponds to setting/clearing Bit 1 of IRQSTA and
IRQSIG.
0
Reserved.
Any interrupt signal must be active for at least the minimum
interrupt latency time to be detected by the interrupt controller
and to be detected by the user in the IRQSTA/FIQSTA register.
VECTORED INTERRUPT CONTROLLER (VIC)
Each ADuC706x incorporates an enhanced interrupt control
system or vectored interrupt controller. The vectored interrupt
controller for IRQ interrupt sources is enabled by setting Bit 0
of the IRQCONN register. Similarly, Bit 1 of IRQCONN enables
the vectored interrupt controller for the FIQ interrupt sources.
The vectored interrupt controller provides the following
enhancements to the standard IRQ/FIQ interrupts:
Vectored interrupts—allows a user to define separate
interrupt service routine addresses for every interrupt
source. This is achieved by using the IRQBASE and
IRQVEC registers.
IRQ/FIQ interrupts—can be nested up to eight levels
depending on the priority settings. An FIQ still has a
higher priority than an IRQ. Therefore, if the VIC is
enabled for both the FIQ and IRQ and prioritization is
maximized, it is possible to have 16 separate interrupt
levels.
Programmable interrupt priorities—using the IRQP0 to
IRQP2 registers, an interrupt source can be assigned an
interrupt priority level value from 0 to 7.
VIC MMRS
IRQBASE
The vector base register, IRQBASE, is used to point to the start
address of memory used to store 32 pointer addresses. These
pointer addresses are the addresses of the individual interrupt
service routines.
IRQBASE Register
Name:
IRQBASE
Address:
0xFFFF0014
Default value: 0x00000000
Access:
Read and write
Table 67. IRQBASE MMR Bit Designations
Bit
Access
Initial Value
Description
31:16
Read only
Reserved
Always read as 0.
15:0
R/W
0
Vector base address.
IRQVEC
The IRQ interrupt vector register, IRQVEC, points to a memory
address containing a pointer to the interrupt service routine of
the currently active IRQ. This register should be read only when
an IRQ occurs and IRQ interrupt nesting has been enabled by
setting Bit 0 of the IRQCONN register.
IRQVEC Register
Name:
IRQVEC
Address:
0xFFFF001C
Default value: 0x00000000
Access:
Read only
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