參數(shù)資料
型號： ADUC7060BSTZ32-RL
廠商： Analog Devices Inc
文件頁數(shù)： 39/108頁
文件大?。?/td> 0K
描述： IC ARM7 MCU FLASH 32K 48LQFP
產(chǎn)品變化通告： ADuC7060/1 Idd Specification Change 01/Feb/2010
設(shè)計資源： 4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145)
Low power, Long Range, ISM Wireless Measuring Node (CN0164)
標準包裝： 2,000
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 10MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 14
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
RAM 容量： 1K x 32
電壓 - 電源 (Vcc/Vdd)： 2.375 V ~ 2.625 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 5x24b，8x24b，D/A 1x14b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 48-LQFP
包裝： 帶卷 (TR)
ADuC7060/ADuC7061
Data Sheet
Rev. D | Page 36 of 108
POWKEY2 Register
Name:
POWKEY2
Address:
0xFFFF040C
Default value:
0xXXXX
Access:
Write
Function:
When writing to POWCON0,
the value of 0xF4 must be
written to this register in the
instruction immediately
before writing to POWCON0.
POWKEY3 Register
Name:
POWKEY3
Address:
0xFFFF0434
Default value: 0xXXXX
Access:
Write
Function:
When writing to POWCON1, the value of
0x76 must be written to this register in the
instruction immediately before writing to
POWCON1.
POWCON1 Register
Name:
POWCON1
Address:
0xFFFF0438
Default value:
0x124
Access:
Read and write
Function:
This register controls the clock signal to the
PWM, UART and I2C/SPI blocks.
By disabling the clock to these blocks, power
consumption is reduced.
POWKEY4 Register
Name:
POWKEY4
Address:
0xFFFF043C
Default value: 0xXXXX
Access:
Write
Function:
When writing to POWCON1, the value of
0xB1 must be written to this register in the
instruction immediately after writing to
POWCON1.
Table 32. POWCON1 MMR Bit Designations
Bit
Name
Description
15:9
Reserved
This bit must always be set to 0.
8
PWMOFF
PWM power-down bit.
Set by user to 1 to enable the PWM block. This bit is set by default.
Cleared by user to 0 to power down the PWM block.
7:6
Reserved
Reserved bits. Always clear these bits to 0.
5
UARTOFF
UART power-down bit.
Set by user to 1 to enable the UART block. This bit is set by default.
Cleared by user to 0 to power down the UART block.
4:3
Reserved
Reserved bits. Always clear these bits to 0.
2
I2CSPIOFF
I2C/SPI power-down bit.
Set by user to 1 to enable the I2C/SPI blocks. This bit is set by default.
Cleared by user to 0 to power down the I2C/SPI blocks.
1:0
Reserved
Reserved Bits. Always clear these bits to 0.
Table 33. ADuC706x Power Saving Modes
POWCON0[6:3]
Mode
Core
Peripherals
PLL
XTAL/T1/T2
IRQ0 to IRQ3
Start-Up/Power-On Time
1111
Active
Yes
130 ms at CD = 0
1110
Pause
Yes
4.8 μs at CD = 0; 660 μs at CD = 7
1100
Nap
Yes
4.8 μs at CD = 0; 660 μs at CD = 7
1000
Sleep
Yes
66 μs at CD = 0; 900 μs at CD = 7
0000
Stop
Yes
66 μs at CD = 0; 900 μs at CD = 7
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