參數(shù)資料
型號: ADSP-BF535
廠商: Analog Devices, Inc.
英文描述: Blackfin Embedded Processor
中文描述: Blackfin嵌入式處理器
文件頁數(shù): 6/44頁
文件大小: 1388K
代理商: ADSP-BF535
ADSP-BF535
–6–
REV. A
Booting
The ADSP-BF535 Blackfin processor contains a small boot
kernel, which configures the appropriate peripheral for booting.
If the ADSP-BF535 Blackfin processor is configured to boot from
boot ROM memory space, the processor starts executing from
the on-chip boot ROM. For more information, see
Booting
Modes on Page 14
.
Event Handling
The event controller on the ADSP-BF535 Blackfin processor
handles all asynchronous and synchronous events to the proces-
sor. The ADSP-BF535 Blackfin processor provides event
handling that supports both nesting and prioritization. Nesting
allows multiple event service routines to be active simultaneously.
Prioritization ensures that servicing of a higher-priority event
takes precedence over servicing of a lower priority event. The
controller provides support for five different types of events:
Emulation—An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
Reset—This event resets the processor.
Non-Maskable Interrupt (NMI)—The NMI event can be
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly
shutdown of the system.
Exceptions—Events that occur synchronously to program
flow, for example, the exception will be taken before the
instruction is allowed to complete. Conditions such as
data alignment violations, undefined instructions, and so
on, cause exceptions.
Interrupts—Events that occur asynchronously to
program flow. They are caused by timers, peripherals,
input pins, explicit software instructions, and so on.
Each event has an associated register to hold the return address
and an associated return-from-event instruction. The state of the
processor is saved on the supervisor stack, when an event is
triggered.
The ADSP-BF535 Blackfin processor event controller consists
of two stages, the Core Event Controller (CEC) and the System
Interrupt Controller (SIC). The Core Event Controller works
with the System Interrupt Controller to prioritize and control all
system events. Conceptually, interrupts from the peripherals
enter into the SIC, and are then routed directly into the general-
purpose interrupts of the CEC.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest priority inter-
rupts (IVG15–14) are recommended to be reserved for software
interrupt handlers, leaving seven prioritized interrupt inputs to
support the peripherals of the ADSP-BF535 Blackfin processor.
Table 1
describes the inputs to the CEC, identifies their names
in the Event Vector Table (EVT), and lists their priorities.
System Interrupt Controller (SIC)
The System Interrupt Controller provides the mapping and
routing of events from the many peripheral interrupt sources to
the prioritized general-purpose interrupt inputs of the CEC.
Although the ADSP-BF535 Blackfin processor provides a default
mapping, the user can alter the mappings and priorities of
interrupt events by writing the appropriate values into the
Interrupt Assignment Registers (IAR).
Table 2
describes the
inputs into the SIC and the default mappings into the CEC.
Table 1. Core Event Controller (CEC)
Priority
(0 is Highest)
Event Class
EVT Entry
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Emulation/Test
Reset
Non-Maskable
Exceptions
Global Enable
Hardware Error
Core Timer
General Interrupt 7
General Interrupt 8
General Interrupt 9
General Interrupt 10
General Interrupt 11
General Interrupt 12
General Interrupt 13
General Interrupt 14
General Interrupt 15
EMU
RST
NMI
EVX
IVHW
IVTMR
IVG7
IVG8
IVG9
IVG10
IVG11
IVG12
IVG13
IVG14
IVG15
Table 2. System Interrupt Controller (SIC)
Peripheral Interrupt
Event
Peripheral
Interrupt ID
Default
Mapping
Real-Time Clock
Reserved
USB
PCI Interrupt
SPORT 0 Rx DMA
SPORT 0 Tx DMA
SPORT 1 Rx DMA
SPORT 1 Tx DMA
SPI 0 DMA
SPI 1 DMA
UART 0 Rx
UART 0 Tx
UART 1 Rx
UART 1 Tx
Timer 0
Timer 1
Timer 2
GPIO Interrupt A
GPIO Interrupt B
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
IVG7
IVG7
IVG7
IVG8
IVG8
IVG8
IVG8
IVG9
IVG9
IVG10
IVG10
IVG10
IVG10
IVG11
IVG11
IVG11
IVG12
IVG12
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ADSP-BF535PBBZ-200 功能描述:IC DSP CONTROLLER 16BIT 260-BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP(數(shù)字式信號處理器) 系列:Blackfin® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI,以太網(wǎng),RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA(20x20) 包裝:托盤
ADSPBF535PKB300 制造商:Analog Devices 功能描述:
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