參數(shù)資料
型號(hào)： ADSP-21160NCB-TBD
廠商： Analog Devices, Inc.
元件分類： 基準(zhǔn)電壓源/電流源
英文描述： Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection
中文描述： 無(wú)電容，NMOS管，150mA的低壓差穩(wěn)壓器的反向電流保護(hù)
文件頁(yè)數(shù)： 6/53頁(yè)
文件大小： 1680K
代理商： ADSP-21160NCB-TBD
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
6
REV. PrB
For current information contact Analog Devices at 800/262-5643
ADSP-21160N
April 2002
PRELIMINARY TECHNICAL DATA
cally transferred to and from on-chip memory via a
dedicated DMA. Each of the serial ports offers a TDM
multichannel mode. The serial ports can operate with lit-
tle-endian or big-endian transmission formats, with word
lengths selectable from 3 bits to 32 bits. They offer selectable
synchronization and transmit modes as well as optional
μ-law or A-law companding. Serial port clocks and frame
syncs can be internally or externally generated.
Host Processor Interface
The ADSP-21160N host interface allows easy connection
to standard microprocessor buses, both 16-bit and 32-bit,
with little additional hardware required. The host interface
is accessed through the ADSP-21160N’s external port and
is memory-mapped into the unified address space. Four
channels of DMA are available for the host interface; code
and data transfers are accomplished with low software
overhead. The host processor communicates with the
ADSP-21160M’s external bus with host bus request
(
HBR
), host but grant (
HBG
), ready (REDY), acknowledge
(ACK), and chip select (CS) signals. The host can directly
read and write the internal memory of the ADSP-21160N,
and can access the DMA channel setup and mailbox regis-
ters. Vector interrupt support provides efficient execution
of host commands.
Program Booting
The internal memory of the ADSP-21160N can be booted
at system power-up from an 8-bit EPROM, a host proces-
sor, or through one of the link ports. Selection of the boot
source is controlled by the
BMS
(Boot Memory Select),
EBOOT (EPROM Boot), and LBOOT (Link/Host Boot)
pins. 32-bit and 16-bit host processors can be used
for booting.
Phased Locked Loop
The ADSP-21160N uses an on-chip PLL to generate the
internal clock for the core. Ratios of 2:1, 3:1, and 4:1
between the core and CLKIN are supported. The
CLK_CFG pins are used to select the ratio. The CLKIN
rate is the rate at which the synchronous external
port operates.
Power Supplies
The ADSP-21160N has separate power supply connections
for the internal (V
DDINT
), external (V
DDEXT
), and analog
(AV
DD
/AGND) power supplies. The internal and analog
supplies must meet the 1.9 V requirement. The external
supply must meet the 3.3 V requirement. All external supply
pins must be connected to the same supply.
The PLL Filter
Figure 5 on page 7
must be added for each
ADSP-21160N in the system. VDDint is the digital core
supply. It is recommended that the capacitors be connected
directly to AGND using short thick trace. It is recom-
mended that the capacitors be placed as close to AVDD and
AGND as possible. The connection from AGND to the
(digital) ground plane should be made after the capacitors.
The use of a thick trace for AGND is reasonable only
because the PLL is a relatively low power circuit - it does
not apply to any other ADSP-21160N GND connection.
Figure 4. Shared Memory Multiprocessing System
ADDR31–0
PA
BMS
PAGE
C
ADSP-21160#1
5
PA
CONTROL
ADSP-21160#2
ADDR31–0
PA
CONTROL
ADSP-21160#3
5
ID2–0
RESET
RPBA
CLKIN
ID2–0
RESET
RPBA
ID2–0
RESET
RPBA
CLKIN
ADSP-21160#6
ADSP-21160#5
ADSP-21160#4
CLOCK
RESET
ADDR
DATA
HOSTPROCESSOR
INTERFACE(OPTIONAL)
ACK
CS
GLOBALMEMORY
AND
PERPHERAL(OPTIONAL)
OE
WE
ADDR
DATA
CS
ADDR
DATA
BOOTEPROM(OPTIONAL)
RDx
WRx
MS3–0
SBTS
CLKOUT
CS
HBR
ACK
ADDR31–0
CLKIN
3
001
3
010
3
011
BR1
BR2–6
REDY
HBG
5
C
A
D
C
A
D
DATA63–0
BR1–2
,
BR4–6
BR3
DATA63–0
BR1
,
BR3–6
BR2
DATA63–0
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