參數(shù)資料
型號(hào)： ADSP-21161NCCA-100
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： DSP Microcomputer
中文描述： 48-BIT, 27.5 MHz, OTHER DSP, PBGA225
封裝： 17 X 17 MM, MO-192AAF-2, BGA-225
文件頁數(shù)： 1/60頁
文件大小： 1019K
代理商： ADSP-21161NCCA-100
a
DSP Microcomputer
ADSP-21161N
S
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
REV. A
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
SUMMARY
High Performance 32-Bit DSP—Applications in Audio,
Medical, Military, Wireless Communications,
Graphics, Imaging, Motor-Control, and Telephony
Super Harvard Architecture—Four Independent Buses
for Dual Data Fetch, Instruction Fetch, and
Nonintrusive, Zero-Overhead I/O
Code Compatible with All Other SHARC Family DSPs
Single-Instruction-Multiple-Data (SIMD) Computational
Architecture—Two 32-Bit IEEE Floating-Point
Computation Units, Each with a Multiplier, ALU,
Shifter, and Register File
Serial Ports Offer I
2
S Support Via 8 Programmable and
Simultaneous Receive or Transmit Pins, which
Support up to 16 Transmit or 16 Receive Channels of
Audio
Integrated Peripherals—Integrated I/O Processor,
1M Bit On-Chip Dual-Ported SRAM, SDRAM
Controller, Glueless Multiprocessing Features, and
I/O Ports (Serial, Link, External Bus, SPI, and JTAG)
ADSP-21161N Supports 32-Bit Fixed, 32-Bit Float, and
40-Bit Floating-Point Formats
KEY FEATURES
100 MHz (10 ns) Core Instruction Rate
Single-Cycle Instruction Execution, Including SIMD
Operations in Both Computational Units
600 MFLOPs Peak and 400 MFLOPs Sustained
Performance
225-Ball 17 mm
×
17 mm MBGA Package
FUNCTIONAL BLOCK DIAGRAM
ALU
MULT
DATA
REGISTER
FILE
(PEY)
16
40-BIT
BARREL
SHIFTER
BARREL
SHIFTER
ALU
DATA
REGISTER
FILE
(PEX)
16
40-BIT
TIMER
INSTRUCTION
CACHE
32
48-BIT
DAG1
4
8
32
PROGRAM
SEQUENCER
32
PM ADDRESS BUS
DM ADDRESS BUS
32
BUS
CONNECT
(PX)
PM DATA BUS
DM DATA BUS
64
64
CORE PROCESSOR
SPI PORTS (1)
SERIAL PORTS (4)
LINK PORTS (2)
DMA
CONTROLLER
5
16
20
4
IOP
REGISTERS
(MEMORY MAPPED)
CONTROL,
STATUS, &
DATA BUFFERS
I/O PROCESSOR
TWO INDEPENDENT
DUAL-PORTED BLOCKS
ADDR
DATA
DATA
DATA
ADDR
ADDR
DATA
ADDR
PROCESSOR PORT
I/O PORT
B
B
DUAL-PORTED SRAM
HOST PORT
ADDR BUS
MUX
MULTIPROCESSOR
INTERFACE
DATA BUS
MUX
32
24
EXTERNAL PORT
6
12
8
JTAG TEST
AND EMULATION
GPIO
FLAGS
SDRAM
CONTROLLER
IOA
18
IOD
64
DAG2
4
8
32
MULT
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700
Fax:781/326-8703
www.analog.com
相關(guān)PDF資料
PDF描述
ADSP-21161NKCA-100 DSP Microcomputer
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ADSP-21161NKCA-100Z 制造商:Analog Devices 功能描述:
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