- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374033 > ADSP-21161NCCA-100 (ANALOG DEVICES INC) DSP Microcomputer PDF資料下載
參數(shù)資料
| 型號： | ADSP-21161NCCA-100 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | 48-BIT, 27.5 MHz, OTHER DSP, PBGA225 |
| 封裝： | 17 X 17 MM, MO-192AAF-2, BGA-225 |
| 文件頁數(shù)： | 13/60頁 |
| 文件大?。?/td> | 1019K |
| 代理商： | ADSP-21161NCCA-100 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當(dāng)前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁
–13–
REV. A
ADSP-21161N
WR
I/O/T
Memory Write Low Strobe.
WR
is asserted when ADSP-21161N writes a word to external
memory or IOP registers of other ADSP-21161Ns. External devices must assert
WR
for
writing to ADSP-21161N IOP registers. In a multiprocessing system, the bus master drives
WR
.
WR
has a 20 k
internal pull-up resistor that is enabled for DSPs with ID2
–
0=00x.
Sequential Burst Access.
BRST is asserted by ADSP-21161N to indicate that data
associated with consecutive addresses is being read or written. A slave device samples the
initial address and increments an internal address counter after each transfer. The incre-
mented address is not pipelined on the bus. A master ADSP-21161N in a multiprocessor
environment can read slave external port buffers (EPBx) using the burst protocol. BRST is
asserted after the initial access of a burst transfer. It is asserted for every cycle after that,
except for the last data request cycle (denoted by
RD
or
WR
asserted and BRST negated).
A keeper latch on the DSP’s BRST pin maintains the input at the level it was last driven.
This latch is only enabled on the ADSP-21161N with ID2
–
0=00x.
Memory Acknowledge.
External devices can de-assert ACK (low) to add wait states to an
external memory access. ACK is used by I/O devices, memory controllers, or other periph-
erals to hold off completion of an external memory access. The ADSP-21161N deasserts
ACK as an output to add wait states to a synchronous access of its IOP registers. ACK has
a 20 k
internal pull-up resistor that is enabled during reset or on DSPs with ID2
–
0=00x.
Suspend Bus and Three-State.
External devices can assert
SBTS
(low) to place the
external bus address, data, selects, and strobes in a high impedance state for the following
cycle. If the ADSP-21161N attempts to access external memory while
SBTS
is asserted, the
processor will halt and the memory access will not be completed until
SBTS
is deasserted.
SBTS
should only be used to recover from host processor/ADSP-21161N deadlock.
SDRAM Column Access Strobe.
In conjunction with
RAS
,
MSx
,
SDWE
, SDCLKx,
and sometimes SDA10, defines the operation for the SDRAM to perform.
SDRAM Row Access Strobe.
In conjunction with
CAS
,
MSx
,
SDWE
, SDCLKx, and
sometimes SDA10, defines the operation for the SDRAM to perform.
SDRAM Write Enable.
In conjunction with
CAS
,
RAS
,
MSx
, SDCLKx, and sometimes
SDA10, defines the operation for the SDRAM to perform.
SDRAM Data Mask.
In write mode, DQM has a latency of zero and is used during a
precharge command and during SDRAM power-up initialization.
SDRAM Clock Output 0.
Clock for SDRAM devices.
SDRAM Clock Output 1.
Additional clock for SDRAM devices. For systems with multiple
SDRAM devices, handles the increased clock load requirements, eliminating need of off-
chip clock buffers. Either SDCLK1 or both SDCLKx pins can be three-stated.
SDRAM Clock Enable.
Enables and disables the CLK signal. For details, see the data
sheet supplied with the SDRAM device.
SDRAM A10 Pin.
Enables applications to refresh an SDRAM in parallel with a non-
SDRAM accesses or host accesses. This pin replaces the DSP’s A10 pin only during SDRAM
accesses.
Interrupt Request Lines.
These are sampled on the rising edge of CLKIN and may be
either edge-triggered or level-sensitive.
Flag Pins.
Each is configured via control bits as either an input or output. As an input, it
can be tested as a condition. As an output, it can be used to signal external peripherals.
Timer Expired.
Asserted for four core clock cycles when the timer is enabled and
TCOUNT decrements to zero.
Host Bus Request.
Must be asserted by a host processor to request control of the ADSP-
21161N’s external bus. When
HBR
is asserted in a multiprocessing system, the ADSP-
21161N that is bus master will relinquish the bus and assert
HBG
. To relinquish the bus,
the ADSP-21161N places the address, data, select, and strobe lines in a high impedance
state.
HBR
has priority over all ADSP-21161N bus requests (
BR6–1
) in a multiprocessing
system.
BRST
I/O/T
ACK
I/O/S
SBTS
I/S
CAS
I/O/T
RAS
I/O/T
SDWE
I/O/T
DQM
O/T
SDCLK0
SDCLK1
I/O/S/T
O/S/T
SDCKE
I/O/T
SDA10
O/T
IRQ2–0
I/A
FLAG11
–
0
I/O/A
TIMEXP
O
HBR
I/A
Table 2. Pin Function Descriptions (continued)
Pin
Type
Function
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADSP-21161NKCA-100 | DSP Microcomputer |
| ADSP-21262SBBC-150 | Embedded Processor |
| ADSP-21262SBBCZ150 | Embedded Processor |
| ADSP-21262SKSTZ200 | SHARC Processor |
| ADSP-21262 | SHARC Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-21161NCCAZ100 | 功能描述:IC DSP CONTROLLER 32BIT 225MBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21161NKCA-100 | 功能描述:IC DSP CONTROLLER 32BIT 225MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21161NKCA-100Z | 制造商:Analog Devices 功能描述: |
| ADSP-21161NKCAZ100 | 功能描述:IC DSP CONTROLLER 32BIT 225MBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21161NYCAZ110 | 功能描述:IC DSP CONTROLLER 32BIT 225BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。