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| 型號(hào)： | ADSP-21160NCB-TBD |
| 廠商： | Analog Devices, Inc. |
| 元件分類(lèi)： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
| 中文描述： | 無(wú)電容，NMOS管，150mA的低壓差穩(wěn)壓器的反向電流保護(hù) |
| 文件頁(yè)數(shù)： | 24/53頁(yè) |
| 文件大?。?/td> | 1680K |
| 代理商： | ADSP-21160NCB-TBD |
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PRELIMINARY TECHNICAL DATA
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
24
REV. PrB
For current information contact Analog Devices at 800/262-5643
ADSP-21160N
April 2002
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-21160N is the bus master accessing external memory space in asyn-
chronous access mode. Note that timing for ACK, DATA,
RDx
,
WRx
, and
DMAG
strobe timing parameters only applies
to asynchronous access mode.
Table 10. Memory Read—Bus Master
Parameter
Timing Requirements:
t
DAD
Min
Max
Unit
Address,
CIF
, Selects Delay to Data
Valid
1,2
RDx
Low to Data Valid
1,3
Data Hold from Address, Selects
4
Data Setup to
RDx
High
1
Data Hold from
RDx
High
3,4
ACK Delay from Address, Selects
2,5
ACK Delay from
RDx
Low
3,5
ACK Setup to CLKIN
3,5
ACK Hold After CLKIN
3
Switching Characteristics:
t
DRHA
Address,
CIF
, Selects Hold After
RDx
High
3
t
DARL
Address,
CIF
, Selects to
RDx
Low
2
t
RW
RDx
Pulse width
3
t
RWR
RDx
High to
WRx
,
RDx
,
DMAGx
Low
3
W = (number of wait states specified in WAIT register) t
CK
.
HI = t
CK
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = t
CK
(if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
1
Data Delay/Setup: User must meet t
DAD
, t
DRLD
, or t
SDS.
2
The falling edge of
MSx
,
BMS
is referenced.
3
Note that timing for ACK, DATA,
RDx
,
WRx
, and
DMAG
strobe timing parameters only applies to asynchronous access mode.
4
Data Hold: User must meet t
HDA
or t
HDRH
in asynchronous access mode. See
Example System Hold Time Calculation on page 47
for the calculation of
hold times given capacitive and dc loads.
5
ACK Delay/Setup: User must meet t
DAAK
, t
DSAK
, or t
SAKC
for deassertion of ACK (Low), all three specifications must be met for assertion of ACK (High).
t
CK
–0.25t
CCLK
–11+W
ns
t
DRLD
t
HDA
t
SDS
t
HDRH
t
DAAK
t
DSAK
t
SAKC
t
HAKC
t
CK
–0.5t
CCLK
+W
ns
ns
ns
ns
ns
ns
ns
ns
0
8
1
t
CK
–0.5t
CCLK
–12+W
t
CK
–0.75t
CCLK
–11+W
0.5t
CCLK
+3
1
0.25t
CCLK
–1+H
ns
0.25t
CCLK
–3
t
CK
–0.5t
CCLK
–1+W
0.5t
CCLK
–1+HI
ns
ns
ns
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