參數(shù)資料
型號(hào)： ADSP-21160NCB-TBD
廠商： Analog Devices, Inc.
元件分類： 基準(zhǔn)電壓源/電流源
英文描述： Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection
中文描述： 無電容，NMOS管，150mA的低壓差穩(wěn)壓器的反向電流保護(hù)
文件頁(yè)數(shù)： 35/53頁(yè)
文件大?。?/td> 1680K
代理商： ADSP-21160NCB-TBD
PRELIMINARY TECHNICAL DATA
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
35
REV. PrB
For current information contact Analog Devices at 800/262-5643
ADSP-21160N
April 2002
Three-State Timing—Bus Master and Bus Slave
These specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to
CLKIN and the
SBTS
pin. This timing is applicable to bus master transition cycles (BTC) and host transition cycles (HTC)
as well as the
SBTS
pin.
Table 17. Three-State Timing—Bus Slave,
HBR
,
SBTS
Parameter
Timing Requirements:
t
STSCK
t
HTSCK
Switching Characteristics:
t
MIENA
Address/Select Enable After CLKIN
t
MIENS
Strobes Enable After CLKIN
1
t
MIENHG
HBG
Enable After CLKIN
t
MITRA
Address/Select Disable After CLKIN
t
MITRS
Strobes Disable After CLKIN
1,2
t
MITRHG
HBG
Disable After CLKIN
t
DATEN
Data Enable After CLKIN
3
t
DATTR
Data Disable After CLKIN
3
t
ACKEN
ACK Enable After CLKIN
3
t
ACKTR
ACK Disable After CLKIN
3
t
CDCEN
CLKOUT Enable After CLKIN
t
CDCTR
CLKOUT Disable After CLKIN
t
ATRHBG
Address,
MSx
Disable Before
HBG
Low
t
STRHBG
RDx
,
WRx
,
DMAGx
Disable Before
HBG
Low
t
PTRHBG
Page Disable Before
HBG
Low
t
BTRHBG
BMS
Disable Before
HBG
Low
t
MENHBG
Memory Interface Enable After HBG High
4
Min
Max
Unit
SBTS
Setup Before CLKIN
SBTS
Hold After CLKIN
6
2
ns
ns
1.5
1.5
1.5
1.5
0.25t
CCLK
–4
3.5
0.25t
CCLK
+1
1.5
1.5
1.5
1.5
t
CCLK
–3
1.5t
CK
+ 1.5
t
CK
+ 0.25t
CCLK
+ 1.5
t
CK
+ 1.5
0.5t
CK
+ 1.5
t
CK
–5
9
9
9
9
0.25t
CCLK
8
0.25t
CCLK
+7
5
9
5
9
t
CCLK
+1
1.5t
CK
+ 5
t
CK
+ 0.25t
CCLK
+ 5
t
CK
+ 5
0.5t
CK
+ 1.5
t
CK
+5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
Strobes =
RDx
,
WRx
,
DMAG
x.
2
If access aborted by
SBTS
, then strobes disable
before
CLKIN [0.25t
CCLK
+ 1.5 (min.), 0.25t
CCLK
+ 5 (max.)]
3
In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.
4
Memory Interface = Address,
RDx
,
WRx
,
MSx
, PAGE,
DMAGx
, and
BMS
(in EPROM boot mode).
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