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| 型號： | ADSP-21160NCB-TBD |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
| 中文描述： | 無電容，NMOS管，150mA的低壓差穩(wěn)壓器的反向電流保護 |
| 文件頁數(shù)： | 27/53頁 |
| 文件大小： | 1680K |
| 代理商： | ADSP-21160NCB-TBD |
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PRELIMINARY TECHNICAL DATA
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
27
REV. PrB
For current information contact Analog Devices at 800/262-5643
ADSP-21160N
April 2002
Synchronous Read/Write—Bus Master
Use these specifications for interfacing to external memory systems that require CLKIN—relative timing or for accessing
a slave ADSP-21160N (in multiprocessor memory space). These synchronous switching characteristics are also valid during
asynchronous memory reads and writes except where noted (see
Memory Read—Bus Master on page 24
and
Memory
Write—Bus Master on page 26
). When accessing a slave ADSP-21160N, these switching characteristics must meet the
slave’s timing requirements for synchronous read/writes (see
Synchronous Read/Write—Bus Slave on page 29
). The slave
ADSP-21160N must also meet these (bus master) timing requirements for data and acknowledge setup and hold times.
Table 12. Synchronous Read/Write—Bus Master
Parameter
Timing Requirements:
t
SSDATI
t
HSDATI
t
SACKC
t
HACKC
Switching Characteristics:
t
DADDO
t
HADDO
t
DPGO
t
DRDO
t
DWRO
t
DRWL
t
DDATO
t
HDATO
t
DACKMO
t
ACKMTR
t
DCKOO
t
CKOP
t
CKWH
t
CKWL
Min
Max
Unit
Data Setup Before CLKIN
1
Data Hold After CLKIN
1
ACK Setup Before CLKIN
1
ACK Hold After CLKIN
1
1
Note that timing for ACK, DATA,
RDx
,
WRx
, and
DMAG
strobe timing parameters only applies to synchronous access mode.
2
Applies to broadcast write, master precharge of ACK.
3
Applies only when the DSP drives a bus operation; CLKOUT held inactive or three-state otherwise, For more information, see the System Design chapter
in the
ADSP-2116x SHARC DSP Hardware Reference
.
5.5
1
0.5t
CCLK
+3
1
ns
ns
ns
ns
Address,
MS
x,
BMS
, BRST,
CIF
Delay After CLKIN
Address,
MS
x,
BMS
, BRST,
CIF
Hold After CLKIN
PAGE Delay After CLKIN
RDx
High Delay After CLKIN
1
WRx
High Delay After CLKIN
1
RDx
/
WRx
Low Delay After CLKIN
Data Delay After CLKIN
Data Hold After CLKIN
ACK Delay After CLKIN
2
ACK Disable Before CLKIN
2
CLKOUT Delay After CLKIN
CLKOUT Period
CLKOUT Width High
CLKOUT Width Low
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.5
1.5
0.25t
CCLK
–1
0.25t
CCLK
–1
0.25t
CCLK
–1
11
0.25t
CCLK
+9
0.25t
CCLK
+9
0.25t
CCLK
+9
0.25t
CCLK
+9
1.5
3
–3
1
t
CK
–1
t
CK
/2–2
t
CK
/2–2
9
5
t
CK
3
+1
t
CK
/2+2
3
t
CK
/2+2
3
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