參數(shù)資料
型號(hào): ADS62C17IRGCT
廠商: Texas Instruments
文件頁(yè)數(shù): 52/68頁(yè)
文件大?。?/td> 0K
描述: IC ADC 11BIT DUAL 200MSPS 64VQFN
標(biāo)準(zhǔn)包裝: 1
位數(shù): 11
采樣率(每秒): 200M
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 1.1W
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 64-VQFN 裸露焊盤(pán)(9x9)
包裝: 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類型: 2 個(gè)差分,單極
產(chǎn)品目錄頁(yè)面: 888 (CN2011-ZH PDF)
其它名稱: 296-24232-6
Whenthe “High” switchesareclosed , OUTP = 1.375 V, OUTM = 1.025 V
Whenthe “Low” switchesareclosed , OUTP = 1.025 V, OUTM = 1.375 V
Switchimpedanceis
nominally 50 W (+/- 10%)
Whenthe “High” (or “Low”) switchesareclosed, Rout = 100 W
1.2 V
+ 0.35 V
- 0.35 V
OUTP
OUTM
Rout
ADS62C18
Low
High
Low
High
Parallel CMOS Interface
SLAS631A – APRIL 2009 – REVISED JULY 2009 ............................................................................................................................................................. www.ti.com
Figure 59. LVDS Buffer Equivalent Circuit
In the CMOS mode, each data bit is output on separate pin as CMOS voltage level, every clock cycle. The rising
edge of the output clock CLKOUT can be used to latch data in the receiver (for sampling frequencies up to
150 MSPS).
Up to 150MSPS, the setup and hold timings of the output data with respect to CLKOUT are specified. It is
recommended to minimize the load capacitance seen by data and clock output pins by using short traces to the
receiver. Also, match the output data and clock traces to minimize the skew between them.
For sampling frequencies above 150 MSPS, it is recommended to use an external clock to capture data. The
delay from input clock to output data and the data valid times are specified for the higher sampling frequencies.
These timings can be used to delay the input clock appropriately and use it to capture the data.
56
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS62C17
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