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www.ti.com ............................................................................................................................................................. SLAS631A – APRIL 2009 – REVISED JULY 2009
A7 – A0 IN HEX
D7
D6
D5
D4
D3
D2
D1
D0
6A
<GAIN CORRECTION – CH B> +0.001 dB to +0.134 dB, in 128 steps
Using the FINE GAIN ADJUST register bits, the channel gain can be trimmed in fine steps. The trim is only
additive, has 128 steps & a range of 0.134dB. The relation between the FINE GAIN ADJUST bits & the trimmed
channel gain is:
Δ Channel Gain = 20 × log10[1 + (FINE GAIN ADJUST/8192)]
Note that the total device gain = ADC gain +
Δ Channel gain. The ADC gain is determined by register bits <GAIN
PROGRAMMABILITY>
A7 – A0 IN
D7
D6
D5
D4
D3
D2
D1
D0
HEX
6C
0
0
0
<SNRBoost Enable – CH B>
D0
<SNRBoost Enable – CH B>
SNRBoost control for channel B (only with independent control).
0 SNRBoost disabled
1 SNRBoost enabled
A7 – A0 IN HEX
D7
D6
D5
D4
D3
D2
D1
D0
75
0
<TEST PATTERNS – CH B>
D2-D0
<TEST PATTERNS> Test Patterns to verify data capture
Applies to both channels (with common control) for channel A only (with independent control)
000 Normal operation
001 Outputs all zeros
010 Outputs all ones
Outputs toggle pattern
011
Output data <D10:D0> alternates between 01010101010 and 10101010101 every clock cycle.
Outputs digital ramp
100
Output data increments by one LSB (12-bit) every 8th clock cycle from code 0 to code 2047.
101 Outputs custom pattern (use registers 0x51, 0x52 for setting the custom pattern)
110 Unused
111 Unused
Copyright 2009, Texas Instruments Incorporated
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