參數(shù)資料
型號(hào)： ADS62C17IRGCT
廠商： Texas Instruments
文件頁(yè)數(shù)： 49/68頁(yè)
文件大?。?/td> 0K
描述： IC ADC 11BIT DUAL 200MSPS 64VQFN
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 11
采樣率（每秒）： 200M
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 1.1W
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 64-VQFN 裸露焊盤（9x9）
包裝： 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類型： 2 個(gè)差分，單極
產(chǎn)品目錄頁(yè)面： 888 (CN2011-ZH PDF)
其它名稱： 296-24232-6
Power Down Global
Channel Power Down (individual or both channels)
Output Buffer Disable (individual or both channels)
Input Clock Stop
POWER SUPPLY SEQUENCE
DIGITAL OUTPUT INTERFACE
DDR LVDS Interface
www.ti.com ............................................................................................................................................................. SLAS631A – APRIL 2009 – REVISED JULY 2009
Table 13. Power Down Controls
POWER DOWN MODES
CONFIGURE USING
WAKE-UP
TIME
SERIAL INTERFACE
PARALLEL CONTROL
PINS
Normal operation
<POWER DOWN MODES>=0000
low
–
Output buffer disabled for channel B
<POWER DOWN MODES>=1001
The pins do not
–
support output buffer
Output buffer disabled for channel A
<POWER DOWN MODES>=1010
–
disable
Output buffer disabled for channel A and B
<POWER DOWN MODES>=1011
Fast (100 ns)
Global power down
<POWER DOWN MODES>=1100
high
low
Slow (20
s)
Channel B standby
<POWER DOWN MODES>=1101
high
low
high
Fast (1
s)
Channel A standby
<POWER DOWN MODES>=1110
high
low
Fast (1
s)
Multiplexed (MUX) mode – Output data of channel A
<POWER DOWN MODES>=1111
high
–
and B is multiplexed & available on DA10 to DA0
pins.
In this mode, the entire chip including both the A/D converters, internal reference and the output buffers are
powered down resulting in reduced total power dissipation of about 45mW. The output buffers are in high
impedance state. The wake-up time from the global power down to data becoming valid in normal mode is
typically 20
s.
Here, each channel’s A/D converter can be powered down. The internal references are active, resulting in quick
wake-up time of 1
s. The total power dissipation in standby is about 450 mW.
Each channel’s output buffer can be disabled and put in high impedance state – wakeup time from this mode is
fast, about 100 ns.
In addition to the above, the converter enters a low-power mode when the input clock frequency falls below
1MSPS. The power dissipation is about 275 mW.
During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are
separated in the device.
ADS62C17 provides 11-bit data and an output clock synchronized with the data.
Two output interface options are available – Double Data Rate (DDR) LVDS and parallel CMOS. They can be
selected using the serial interface register bit <LVDS_CMOS> or using DFS pin in parallel configuration mode.
In this mode, the data bits and clock are output using LVDS (Low Voltage Differential Signal) levels. Two data
bits are multiplexed and output on each LVDS differential pair.
Copyright 2009, Texas Instruments Incorporated
53
Product Folder Link(s): ADS62C17
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