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參數(shù)資料
| 型號(hào)： | ADS62C17IRGCT |
| 廠商： | Texas Instruments |
| 文件頁(yè)數(shù)： | 5/68頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ADC 11BIT DUAL 200MSPS 64VQFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 11 |
| 采樣率（每秒）： | 200M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 1.1W |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-VQFN 裸露焊盤（9x9） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸入數(shù)目和類型： | 2 個(gè)差分，單極 |
| 產(chǎn)品目錄頁(yè)面： | 888 (CN2011-ZH PDF) |
| 其它名稱： | 296-24232-6 |
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SERIAL INTERFACE CONFIGURATION ONLY
USING BOTH SERIAL INTERFACE and PARALLEL CONTROLLS
DETAILS OF PARALLEL CONFIGURATION ONLY
www.ti.com ............................................................................................................................................................. SLAS631A – APRIL 2009 – REVISED JULY 2009
To exercise this mode, first the serial registers have to be reset to their default values and RESET pin has to be
kept low.
SEN, SDATA and SCLK function as serial interface pins in this mode and can be used to access the internal
registers of the ADC.
The registers can be reset either by applying a pulse on RESET pin or by setting the <RESET> bit high. The
serial interface section describes the register programming and register reset in more detail.
For increased flexibility, a combination of serial interface registers and parallel pin controls (CTRL1 to CTRL3)
can also be used to configure the device. To allow this, keep RESET low. The parallel interface control pins
CTRL1 to CTRL3 are available. After power-up, the device will automatically get configured as per the voltage
settings on these pins (Table 6). SEN, SDATA, and SCLK function as serial interface digital pins and are used to
access the internal registers of ADC. The registers must first be reset to their default values either by applying a
pulse on RESET pin or by setting bit <RST> = 1. After reset, the RESET pin must be kept low. The serial
interface section describes the register programming and register reset in more detail.
The functions controlled by each parallel pin are described below. A simple way of configuring the parallel pins is
shown in Figure 6.
Table 5. SCLK Control Pin
SCLK
DESCRIPTION
0
Internal reference
+200mV/-0mV
(3/8)AVDD
External reference
±200mV
(5/8)2AVDD
External reference
±200mV
AVDD
Internal reference
+0mV/-200mV
Table 6. SEN Control Pin
SEN
DESCRIPTION
0
Offset binary and DDR LVDS output
+200mV/-0mV
(3/8)AVDD
2’s complement format and DDR LVDS output
±200mV
(5/8)2AVDD
2’s complement format and parallel CMOS output
±200mV
AVDD
Offset binary and parallel CMOS output
+0mV/-200mV
Table 7. CTRL1, CTRL2 and CTRL3 Pins
CTRL1
CTRL2
CTRL3
DESCRIPTION
LOW
Normal operation
LOW
HIGH
SNRBoost enabled for Channel B(1)
LOW
HIGH
LOW
SNRBoost enabled for Channel A(1)
LOW
HIGH
SNRBoost enabled for Channel A and B(1)
HIGH
LOW
Global power down
HIGH
LOW
HIGH
Channel B standby
(1)
To enable & disable SNRBoost mode using the CTRL pins, reset the register bits <SNRBoost Enable -
CHA> = 0 & <SNRBoost Enable - CHB> = 0.
Copyright 2009, Texas Instruments Incorporated
13
Product Folder Link(s): ADS62C17
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