參數(shù)資料
型號: AD9995KCPZ
廠商: Analog Devices Inc
文件頁數(shù): 38/60頁
文件大?。?/td> 0K
描述: IC CCD SIGNAL PROCESSOR 56-LFCSP
標準包裝: 1
類型: CCD 信號處理器,12 位
輸入類型: 邏輯
輸出類型: 邏輯
接口: 3 線串口
電流 - 電源: 30mA
安裝類型: 表面貼裝
封裝/外殼: 56-VFQFN 裸露焊盤,CSP
供應商設備封裝: 56-LFCSP-VQ(8x8)
包裝: 托盤
AD9995
–43–
COMPLETE LISTING FOR REGISTER BANK 2
All V-pattern group and V-sequence registers are SCP updated, and all Field registers are VD updated.
All address and default values are in hexadecimal.
Table XXVI.V-Pattern Group 0 (VPAT0) Register Map
Data Bit Default
Address Content Value
Register Name
Description
00
[5:0]
0
VPOL_0
VPAT0 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5].
[11:6]
0
UNUSED
Unused.
[23:12]
0
VPATLEN_0
Total Length of VPAT0. Note: If using VPAT0 as a second V-sequence in
the VSG active line, this value is the start position for the second V-sequence.
01
[11:0]
0
V1TOG1_0
V1 Toggle Position 1
[23:12]
0
V1TOG2_0
V1 Toggle Position 2
02
[11:0]
0
V1TOG3_0
V1 Toggle Position 3
[23:12]
0
V2TOG1_0
V2 Toggle Position 1
03
[11:0]
0
V2TOG2_0
V2 Toggle Position 2
[23:12]
0
V2TOG3_0
V2 Toggle Position 3
04
[11:0]
0
V3TOG1_0
V3 Toggle Position 1
[23:12]
0
V3TOG2_0
V3 Toggle Position 2
05
[11:0]
0
V3TOG3_0
V3 Toggle Position 3
[23:12]
0
V4TOG1_0
V4 Toggle Position 1
06
[11:0]
0
V4TOG2_0
V4 Toggle Position 2
[23:12]
0
V4TOG3_0
V4 Toggle Position 3
07
[11:0]
0
V5TOG1_0
V5 Toggle Position 1
[23:12]
0
V5TOG2_0
V5 Toggle Position 2
08
[11:0]
0
V5TOG3_0
V5 Toggle Position 3
[23:12]
0
V6TOG1_0
V6 Toggle Position 1
09
[11:0]
0
V6TOG2_0
V6 Toggle Position 2
[23:12]
0
V6TOG3_0
V6 Toggle Position 3
0A
[11:0]
0
FREEZE1_0
V1–V6 Freeze Position 1
[23:12]
0
RESUME1_0
V1–V6 Resume Position 1
0B
[11:0]
0
FREEZE2_0
V1–V6 Freeze Position 2
[23:12]
0
RESUME2_0
V1–V6 Resume Position 2
Table XXVII.V-Pattern Group 1 (VPAT1) Register Map
Data Bit Default
Address Content Value
Register Name
Description
0C
[5:0]
0
VPOL_1
VPAT1 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5].
[11:6]
0
UNUSED
Unused.
[23:12]
0
VPATLEN_1
Total Length of VPAT1. Note: If using VPAT1 as a second V-sequence in
the VSG active line, this value is the start position for the second V-sequence.
0D
[11:0]
0
V1TOG1_1
V1 Toggle Position 1
[23:12]
0
V1TOG2_1
V1 Toggle Position 2
0E
[11:0]
0
V1TOG3_1
V1 Toggle Position 3
[23:12]
0
V2TOG1_1
V2 Toggle Position 1
0F
[11:0]
0
V2TOG2_1
V2 Toggle Position 2
[23:12]
0
V2TOG3_1
V2 Toggle Position 3
10
[11:0]
0
V3TOG1_1
V3 Toggle Position 1
[23:12]
0
V3TOG2_1
V3 Toggle Position 2
11
[11:0]
0
V3TOG3_1
V3 Toggle Position 3
[23:12]
0
V4TOG1_1
V4 Toggle Position 1
12
[11:0]
0
V4TOG2_1
V4 Toggle Position 2
[23:12]
0
V4TOG3_1
V4 Toggle Position 3
REV. 0
OBSOLETE
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