參數(shù)資料
型號(hào)： AD9995KCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 32/60頁(yè)
文件大小： 0K
描述： IC CCD SIGNAL PROCESSOR 56-LFCSP
標(biāo)準(zhǔn)包裝： 1
類型： CCD 信號(hào)處理器，12 位
輸入類型： 邏輯
輸出類型： 邏輯
接口： 3 線串口
電流 - 電源： 30mA
安裝類型： 表面貼裝
封裝/外殼： 56-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 56-LFCSP-VQ（8x8）
包裝： 托盤
AD9995
–38–
Register Address Banks 1 and 2
The AD9995 address space is divided into two different regis-
ter banks, referred to as Register Bank 1 and Register Bank 2.
Figure 41 illustrates how the two banks are divided. Register
Bank 1 contains the registers for the AFE, miscellaneous func-
tions, VD/HD parameters, timing core, CLPOB masking, VSG
patterns, and shutter functions. Register Bank 2 contains all
of the information for the V-pattern groups, V-sequences, and
field information.
AFE REGISTERS
SWITCH TO REGISTER BANK 2
REGISTER BANK 1
ADDR 0x00
ADDR 0x7F
MISCELLANEOUS REGISTERS
VD/HD REGISTERS
TIMING CORE REGISTERS
CLPOB MASK REGISTERS
VSG PATTERN REGISTERS
SHUTTER REGISTERS
ADDR 0x10
ADDR 0x20
ADDR 0x30
ADDR 0x40
ADDR 0x50
ADDR 0x60
VPAT0–VPAT9 REGISTERS
SWITCH TO REGISTER BANK 1
REGISTER BANK 2
ADDR 0x00
VSEQ0–VSEQ9 REGISTERS
FIELD 0–FIELD 5 REGISTERS
ADDR 0x7F
ADDR 0x80
ADDR 0xD0
ADDR 0xFF
ADDR 0x7E
ADDR 0xCF
WRITE TO ADDRESS 0x7F TO SWITCH REGISTER BANKS
ADDR 0xFF
ADDR 0x8F
INVALID—DO NOT ACCESS
Figure 41. Layout of Internal Register Banks 1 and 2
When writing to the AD9995, Address 0x7F is used to specify
which address bank is being written to.To write to Bank 1, the
LSB of Address 0x7F should be set to 0; to write to Bank 2, the
LSB of Address 0x7F should be set to 1.
Note that Register Bank 1 contains many unused addresses. Any
undefined addresses between 0x00 and 0x7F are considered
don’t cares, and it is acceptable if these addresses are filled in
with all 0s during a continuous register write operation. However,
the undefined addresses above 0x7F must not be written to, or
the AD9995 may not operate properly.
REV. 0
OBSOLETE
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