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參數(shù)資料
型號(hào)： AD9995KCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 24/60頁(yè)
文件大?。?/td> 0K
描述： IC CCD SIGNAL PROCESSOR 56-LFCSP
標(biāo)準(zhǔn)包裝： 1
類型： CCD 信號(hào)處理器，12 位
輸入類型： 邏輯
輸出類型： 邏輯
接口： 3 線串口
電流 - 電源： 30mA
安裝類型： 表面貼裝
封裝/外殼： 56-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 56-LFCSP-VQ（8x8）
包裝： 托盤(pán)
AD9995
–30–
AD9995
–31–
DRAFT IMAGE
SERIAL
WRITES
VD
VSG
SUBCK
STROBE
MSHUT
MECHANICAL
SHUTTER
VSUB
CCD
OUT
1
9
10
8
7
6
2
tEXP
4
5
3
OPEN
CLOSED
MODE 0
MODE 1
10
OPEN
STILL IMAGE 3RD FIELD
STILL IMAGE 2ND FIELD
STILL IMAGE 1ST FIELD
DRAFT IMAGE
STILL IMAGE READOUT
Figure 32. Example of Exposure and Still Image Readout Using Shutter Signals and Mode Register
1. Write to the READOUT register (Addr. 0x61) to specify
the number of fields to further suppress SUBCK while the
CCD data is read out. In this example, READOUT = 3.
Write to the EXPOSURE register (Addr. 0x62) to specify
the number of fields to suppress SUBCK and VSG outputs
during exposure. In this example, EXPOSURE = 1.
Write to the TRIGGER register (Addr. 0x60) to enable the
STROBE, MSHUT, and VSUB signals, and to start the
exposure/readout operation.To trigger all of these events (as
in Figure 32), set the register TRIGGER = 31. Readout will
automatically occur after the exposure period is finished.
Write to the MODE register (Addr. 0x1B) to configure the
next five fields.The first two fields during exposure are the
same as the current draft mode fields, and the following
three fields are the still frame readout fields.The registers
for the Draft mode field and the three readout fields have
already been programmed.
2. VD/HD falling edge will update the serial writes from 1.
3. If VSUB mode = 0 (Addr. 0x67),VSUB output turns on at
the line specified in the VSUBON register (Addr. 0x68).
4. STROBE output turns on and off at the location specified
in the STROBEON and OFF registers (Addr. 0x6E to
Addr. 0x71).
5. MSHUT output turns off at the location specified in the
MSHUTOFF registers (Addr. 0x6B and 0x6C).
6. The next VD falling edge will automatically start the first
readout field.
7. The next VD falling edge will automatically start the second
readout field.
8. The next VD falling edge will automatically start the third
readout field.
9. Write to the MODE register to reconfigure the single Draft
mode field timing.
Write to the MSHUTON register (Addr. 0x6A) to open the
mechanical shutter.
10. VD/HD falling edge will update the serial write from 9.
VSG outputs return to Draft mode timing.
SUBCK output resumes operation.
MSHUT output returns to the on position (active or open).
VSUB output returns to the off position (inactive).
EXPOSURE AND READOUT EXAMPLE
REV. 0
OBSOLETE
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