參數(shù)資料
型號(hào)： AD9995KCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 26/60頁(yè)
文件大?。?/td> 0K
描述： IC CCD SIGNAL PROCESSOR 56-LFCSP
標(biāo)準(zhǔn)包裝： 1
類型： CCD 信號(hào)處理器，12 位
輸入類型： 邏輯
輸出類型： 邏輯
接口： 3 線串口
電流 - 電源： 30mA
安裝類型： 表面貼裝
封裝/外殼： 56-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 56-LFCSP-VQ（8x8）
包裝： 托盤
AD9995
–32–
AD9995
–33–
A/D Converter
The AD9995 uses a high performance ADC architecture
optimized for high speed and low power. Differential nonlinearity
(DNL) performance is typically better than 0.5 LSB.The ADC
uses a 2 V input range. See TPC 2 and TPC 3 for typical linearity
and noise performance plots for the AD9995.
Optical Black Clamp
The optical black clamp loop is used to remove residual offsets
in the signal chain and to track low frequency variations in the
CCD’s black level. During the optical black (shielded) pixel inter-
val on each line, the ADC output is compared with a fixed black
level reference, selected by the user in the Clamp Level register.
The value can be programmed between 0 LSB and 255 LSB in
256 steps. The resulting error signal is filtered to reduce noise,
and the correction value is applied to the ADC input through a
D/A converter. Normally, the optical black clamp loop is turned
on once per horizontal line, but this loop can be updated more
slowly to suit a particular application. If external digital clamp-
ing is used during the postprocessing, the AD9995 optical black
clamping may be disabled using Bit D2 in the OPRMODE regis-
ter.When the loop is disabled, the Clamp Level register may still
be used to provide programmable offset adjustment.
The CLPOB pulse should be placed during the CCD’s optical
black pixels. It is recommended that the CLPOB pulse dura-
tion be at least 20 pixels wide to minimize clamp noise. Shorter
pulsewidths may be used, but clamp noise may increase, and the
ability to track low frequency variations in the black level will
be reduced. See the Horizontal Clamping and Blanking section
and the Horizontal Timing Sequence Example section for timing
examples.
Digital Data Outputs
The AD9995 digital output data is latched using the DOUT
PHASE register value, as shown in Figure 33. Output data timing
is shown in Figure 8a. It is also possible to leave the output latches
transparent so that the data outputs are valid immediately from
the A/D converter. Programming the AFE CONTROL register bit
D4 to 1 will set the output latches transparent. The data outputs
can also be disabled (three-stated) by setting the AFE CONTROL
register Bit D3 to 1.
The data output coding is normally straight binary, but the
coding my be changed to gray coding by setting the AFE CON-
TROL register Bit D5 to 1.
REV. 0
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