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| 型號： | AD9979BCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR CCD 14BIT 48-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | CCD 信號處理器，14 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 48mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | AD9979BCPZRLDKR |
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AD9979
Rev. C | Page 15 of 56
Table 8. HCLK Modes (Selected by Register Address 0x23, Bits[7:5])
HCLK Mode
Register Value
Description
Mode 1
001
H1 edges are programmable; H3 = H1, H2 = H4 = inverse of H1.
Mode 2
010
H1 edges are programmable; H3 = H1.
H2 edges are programmable; H4 = H2.
Mode 3
100
H1 edges are programmable; H2 = inverse of H1.
H3 edges are programmable; H4 = inverse of H3.
Invalid Selection
000, 011, 101, 110, 111
Invalid register settings.
Table 9. Horizontal Clock, RG, Drive, and Sample Control Registers Parameters
Name
Length
Range
Description
Polarity
1 bit
High/low
Polarity control for H1/H3 and RG; 0 = no inversion, 1 = inversion
Positive Edge
6 bits
0 to 63 edge location
Positive edge location for H1/H3 and RG
Negative Edge
6 bits
0 to 63 edge location
Negative edge location for H1/H3 and RG
Sample Location
6 bits
0 to 63 sample location
Sampling location for SHP and SHD
Drive Control
3 bits
0 to 7 current steps
Drive current for H1 to H4 and RG outputs (4.3 mA steps)
NOTES
1. EXAMPLE SHOWN FOR SHDLOC = 0.
2. HIGHER VALUES OF SHD AND/OR DOUTPHASE SHIFT DOUT TRANSITION TO THE RIGHT, WITH RESPECT TO CLI LOCATION.
DOUTPHASE
CLK
DOUT
CCDIN
CLI
SHD
(INTERNAL)
ADC OUT
(INTERNAL)
NN+2
N+1
N+3
N+13
N+12
N+11
N+10
N+9
N+7
N+6
N+5
N+4
N+14
SAMPLE PIXEL N
N+16
N+17
N+15
N–14
N–4
N–5
N–6
N–7
N–8
N–10
N–11
N–12
N–13
N–3
N–2
N–1
N
N+1
N–15
N–16
N–17
tCLIDLY
N–4
N–5
N–6
N–7
N–8
N–3
N–2
N–1
N
N+1
tDOUTINH
PIPELINE LATENCY = 16 CYCLES
N–9
N–14
N–10
N–11
N–12
N–13
N–15
N–16
N–17
N–9
N+8
05
95
7-
0
22
Figure 20. Pipeline Delay of AFE Data Outputs
H-Driver and RG Outputs
In addition to the programmable timing positions, the AD9979
features on-chip output drivers for the HL, RG, and H1 to H4
outputs. These drivers are powerful enough to directly drive
the CCD inputs. The H-driver and RG-driver currents can be
adjusted for optimum rise/fall times into a particular load by
using the drive strength control register (Address 0x35). Use
the register to adjust the drive strength in 4.3 mA increments.
The minimum setting of 0 is equal to off or three-state, and the
maximum setting of 7 is equal to 30.1 mA.
Digital Data Outputs
For maximum system flexibility, the AD9979 uses DOUTPHASEN
and DOUTPHASEP (Address 0x37, Bits[11:0]) to select the
location for the start of each new pixel data value. Any edge
location from 0 to 63 can be programmed. Register 0x37
determines the start location of the data output and the
DOUTPHASEx clock rising edge with respect to the master
clock input CLI.
The pipeline delay through the AD9979 is shown in Figure 20.
After the CCD input is sampled by SHD, there is a 16-cycle
delay before the data is available.
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