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| 型號： | AD9979BCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 27/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR CCD 14BIT 48-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | CCD 信號處理器，14 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 48mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | AD9979BCPZRLDKR |
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AD9979
Rev. C | Page 33 of 56
SHA Mode—Differential Input Configuration
In this configuration, which uses a differential input sample-
and- hold amplifier (SHA), a signal is applied to the CCDINP
input, while an inverse signal is applied simultaneously to the
CCDINM input (see Figure 47). Sampling occurs on both
signals at the same time, creating the differential output for
amplification and for the ADC (see Figure 48 and Table 20).
IMAGE
SENSOR
SHA/
CDS
CCDINM
CCDINP
AD9979
05
95
7-
0
49
Figure 47. SHA Mode—Differential Input Configuration
(N + 1) SIGNAL SAMPLE
(N) SIGNAL SAMPLE
POSITIVE INPUT
NEGATIVE INPUT
PEAK SIGNAL
LEVEL (VFS)
BLACK SIGNAL LEVEL (VBLK)
MINIMUM SIGNAL LEVEL (VMIN)
GND
05
95
7-
0
50
Figure 48. SHA Mode—Differential Input Signal
Table 20. SHA Mode—Differential Voltage Levels
Signal Level
Symbol
Min
Typ
Max
Unit
Black Signal Level
VBLK
0
mV
Saturation Signal
Level
VFS
1000
VDD 300
1400
mV
Minimum Signal
Level
VMIN
0
1800
mV
SHA Mode—DC-Coupled, Single-Ended Input
The SHA mode can also be used in a single-ended fashion,
with the signal from the image sensor applied to the CDS/SHA
using a single input, CCDINP. This is similar to the differential
configuration, except in this case, the CCDINM line is held at a
constant dc voltage. This establishes a reference level that matches
the image sensor reference voltage (see Figure 49).
Referring to Figure 50 and Table 21, the CCDINM signal is a
constant dc voltage set at a level above ground potential. The
sensor signal is applied to the other input, and samples are
taken at the signal minimum and at a point of signal maximum.
The resulting differential signal is the difference between the
signal and the reference voltage.
IMAGE
SENSOR
SHA/
CDS
CCDINM
CCDINP
AD9979
NOTES
1. DC VOLTAGE ABOVE GROUND CAN BE USED TO
MATCH THE SENSOR REFERENCE LEVEL.
05
95
7-
0
51
Figure 49. SHA Mode—DC-Coupled, Single-Ended Input Configuration
(N + 1) SIGNAL SAMPLE
(N) SIGNAL SAMPLE
POSITIVE INPUT
NEGATIVE INPUT
PEAK SIGNAL
LEVEL (VFS)
BLACK SIGNAL LEVEL (VBLK)
MINIMUM SIGNAL LEVEL (VMIN)
GND
05
95
7-
0
52
Figure 50. SHA Mode—DC-Coupled, Single-Ended Input Signal
Table 21. SHA Mode—Single-Ended, Input Voltage Levels
Signal Level
Symbol
Min
Typ
Max
Unit
Black Signal Level
VBLK
0
mV
Saturation Signal Level
VFS
1000
1400
mV
Minimum Signal Level
VMIN
0
mV
CDS Timing Control
The timing shown in Figure 19 illustrates how the two internally
generated CDS clocks, SHP and SHD, are used to sample the
reference level and the data level of the CCD signal, respectively.
The placement of the SHP and SHD sampling edges is determined
by the setting of SHPLOC and SHDLOC, located at Address 0x36.
Placement of these two clock signals is critical in achieving the
best performance from the CCD.
SHA Timing Control
When SHA mode is selected, only the SHPLOC setting is used
to sample the input signal, but the SHDLOC signal still needs to
be programmed to an edge setting of SHPLOC + 32.
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