參數(shù)資料
型號： AD9979BCPZRL
廠商： Analog Devices Inc
文件頁數(shù)： 17/56頁
文件大?。?/td> 0K
描述： IC PROCESSOR CCD 14BIT 48-LFCSP
標準包裝： 1
類型： CCD 信號處理器，14 位
輸入類型： 邏輯
輸出類型： 邏輯
接口： 3 線串口
電流 - 電源： 48mA
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 標準包裝
其它名稱： AD9979BCPZRLDKR
AD9979
Rev. C | Page 24 of 56
MODE REGISTERS
To select the final field timing of the AD9979, use the mode
registers. Typically, all of the field and H-pattern group
information is programmed into the AD9979 at startup.
During operation, the mode registers allows the user to
select any combination of field timing to meet the current
requirements of the system. The advantage of using the mode
registers in conjunction with preprogrammed timing is that it
greatly reduces the system programming requirements during
camera operation. Only a few register writes are required when
the camera operating mode is changed, rather than having to
write in all of the vertical timing information with each camera
mode change.
A basic still camera application can require five different fields
of horizontal timing: one for draft mode operation, one for auto
focusing, and three for still-image readout. With the AD9979,
all register timing information for the five fields is loaded at
startup. Then, during camera operation, the mode registers
selects which field timing to activate depending on how the
camera is being used.
The AD9979 supports up to seven field sequences, selected
from up to 31 preprogrammed field groups, using the FIELD_SELx
registers. When FIELDNUM is greater than 1, the AD9979
starts with Field 1 and increments to each Field N at the start of
each VD.
Figure 33 provides examples of the mode configuration settings.
This example assumes having four field groups, Field Group 0
to Field Group 3, stored in memory.
Table 14. Mode Registers
Name
Length
Range
Description
HPATNUM
5 bits
0 to 31 H-pattern groups
Total number of H-pattern groups starting at Address 0x800
FIELDNUM
3 bits
0 to 7 fields
Total number of applied fields (1 = single-field operation)
FIELD_SEL1
5 bits
0 to 31 field groups
Selected first field
FIELD_SEL2
5 bits
0 to 31 field groups
Selected second field
FIELD_SEL3
5 bits
0 to 31 field groups
Selected third field
FIELD_SEL4
5 bits
0 to 31 field groups
Selected fourth field
FIELD_SEL5
5 bits
0 to 31 field groups
Selected fifth field
FIELD_SEL6
5 bits
0 to 31 field groups
Selected sixth field
FIELD_SEL7
5 bits
0 to 31 field groups
Selected seventh field
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