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| 型號： | AD9979BCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR CCD 14BIT 48-LFCSP |
| 標準包裝： | 1 |
| 類型： | CCD 信號處理器，14 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 48mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 標準包裝 |
| 其它名稱： | AD9979BCPZRLDKR |
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AD9979
Rev. C | Page 18 of 56
Individual HBLK Patterns
The HBLK programmable timing shown in Figure 23 is similar
to CLPOB and PBLK; however, there is no start polarity control.
Only the toggle positions designate the start and the stop positions
of the blanking period. Additionally, as shown in Figure 24,
there is a polarity control, HBLKMASK, for H1/H3 and H2/H4
that designates the polarity of the horizontal clock signals
during the blanking period. Setting HBLKMASK_H1 low sets
H1 = H3 = low and HBLKMASK_H2 high sets H2 = H4 = high
during the blanking. As with the CLPOB and PBLK signals,
HBLK registers are available in each H-pattern group, allowing
unique blanking signals to be used with different vertical timing
sequences.
The AD9979 supports three different modes for HBLK
operation. HBLK Mode 0 supports basic operation and offers
some support for special HBLK patterns. HBLK Mode 1
supports pixel mixing HBLK operation. HBLK Mode 2 supports
advanced HBLK operation. The following sections describe
each mode. Register names are detailed in Table 11.
HBLK Mode 0 Operation
There are six toggle positions available for HBLK. Normally,
only two of the toggle positions are used to generate the
standard HBLK interval. However, the additional toggle
positions can be used to generate special HBLK patterns, as
shown in Figure 25. The pattern in this example uses all six
toggle positions to generate two extra groups of pulses during
the HBLK interval. By changing the toggle positions, different
patterns are created.
Separate toggle positions are available for even and odd lines. If
alternation is not needed, load the same values into both the
HBLKTOGEx and HBLKTOGOx registers.
HBLK
SPECIAL HBLK PATTERN IS CREATED USING MULTIPLE HBLK TOGGLE POSITIONS (HBLKALT_PATx = 0).
H1/H3
H2/H4
HBLKTOGE1
HBLKTOGE2
HBLKTOGE3
HBLKTOGE4
HBLKTOGE5
HBLKTOGE6
0
595
7-
0
27
Figure 25. Generating Special HBLK Patterns
Table 11. HBLK Pattern Registers
Name
Length
Range
Description
HBLKMODE
2 bits
0 to 2
Enables different HBLK toggle position operation.
0 = normal mode. Six toggle positions are available for even and odd lines. If even/
odd alternation is not need, set the toggle positions for the even/odd the same.
1 = pixel mixing mode. Instead of only six toggle positions, use the HBLKSTART,
HBLKEND, HBLKLEN, and HBLKREP registers, along with HBLKTOGOx and
HBLKTOGEx. If even/odd alternation is not need, set the even/odd toggles the same.
2 = advanced HBLK mode. It divides HBLK interval into six different repeat areas.
It uses HBLKSTARTA, HBLKSTARTB, HBLKSTARTC, and RAxHyREPA/RAxHyREPB/
RAxHyREPC registers.
3 = test mode. Do not access.
HBLKSTART
13 bits
0 to 8191 pixel location
Start location for HBLK in HBLK Mode 1 and HBLK Mode 2.
HBLKEND
13 bits
0 to 8191 pixel location
End location for HBLK in HBLK Mode 1 and HBLK Mode 2.
HBLKLEN
13 bits
0 to 8191 pixels
HBLK length in HBLK Mode 1 and HBLK Mode 2.
HBLKREP
13 bits
0 to 8191 repetitions
Number of HBLK repetitions in HBLK Mode 1 and HBLK Mode 2.
HBLKMASK_H1
1 bit
High/low
Masking polarity for H1/H3 during HBLK.
HBLKMASK_H2
1 bit
High/low
Masking polarity for H2/H4 during HBLK.
HBLKMASK_HL
1 bit
High/low
Masking polarity for HL during HBLK.
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