參數(shù)資料
型號(hào): AD9912ABCPZ-REEL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 8/40頁(yè)
文件大?。?/td> 0K
描述: IC DDS 1GSPS DAC 14BIT 64LFCSP
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝: 750
分辨率(位): 14 b
主 fclk: 1GHz
調(diào)節(jié)字寬(位): 48 b
電源電壓: 1.8V, 3.3V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤(pán),CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 帶卷 (TR)
AD9912
Rev. F | Page 16 of 40
INPUT/OUTPUT TERMINATION RECOMMENDATIONS
DOWNSTREAM
DEVICE
(HIGH-Z)
AD9912
1.8V
HSTL
OUTPUT
100
06
76
3-
0
27
0.01F
Figure 33. AC-Coupled HSTL Output Driver
DOWNSTREAM
DEVICE
(HIGH-Z)
AD9912
1.8V
HSTL
OUTPUT
50
50
06
76
3-
02
8
AVDD/2
Figure 34. DC-Coupled HSTL Output Driver
AD9912
SELF-BIASING
SYSCLK
INPUT
(CRYSTAL
MODE)
10pF*
06
76
3-
0
29
10pF*
REFER TO CRYSTAL
DATA SHEET.
*
Figure 35. SYSCLK Input, Xtal
AD9912
SELF-BIASING
SYSCLK
INPUT
0.1F
100
06
76
3-
03
0
CLOCK
SOURCE
WITH DIFF.
OUTPUT
Figure 36. SYSCLK Differential Input, Non-Xtal
AD9912
SELF-BIASING
SYSCLK
INPUT
0.01F
06
76
3-
04
9
CLOCK SOURCE
WITH
SINGLE-ENDED
1.8V CMOS
OUTPUT
Figure 37. SYSCLK Single-Ended Input, Non-Xtal
AD9912
SELF-BIASING
FDBK INPUT
0.1F
06
76
3-
05
0
100
(OPTIONAL)
Figure 38. FDBK_IN Input
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