參數(shù)資料
型號: AD9912ABCPZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 32/40頁
文件大小: 0K
描述: IC DDS 1GSPS DAC 14BIT 64LFCSP
產(chǎn)品培訓模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標準包裝: 750
分辨率(位): 14 b
主 fclk: 1GHz
調(diào)節(jié)字寬(位): 48 b
電源電壓: 1.8V, 3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 帶卷 (TR)
AD9912
Rev. F | Page 38 of 40
Register 0x0503—Spur A (Continued)
Table 38.
Bits
Bit Name
Description
[7:0]
Spur A phase
Linear offset for Spur B phase.
Register 0x0504—Spur A (Continued)
Table 39.
Bits
Bit Name
Description
[8]
Spur A phase
Linear offset for Spur A phase.
Register 0x0505—Spur B
Table 40.
Bits
Bit Name
Description
7
HSR-B enable
Harmonic Spur Reduction B enable.
6
Amplitude gain × 2
Setting this bit doubles the gain of the cancelling circuit and also doubles the minimum step size.
[5:4]
Reserved
Reserved.
[3:0]
Spur B harmonic
Spur B Harmonic 1 to Spur B Harmonic 15. Allows user to choose which harmonic to eliminate.
Register 0x0506—Spur B (Continued)
Table 41.
Bits
Bit Name
Description
[7:0]
Spur B magnitude
Linear multiplier for Spur B magnitude.
Register 0x0508—Spur B (Continued)
Table 42.
Bits
Bit Name
Description
[7:0]
Spur B phase
Linear offset for Spur B phase.
Register 0x0509—Spur B (Continued)
Table 43.
Bits
Bit Name
Description
8
Spur B phase
Linear offset for Spur B phase.
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