tHIGH t
參數(shù)資料
型號: AD9912ABCPZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 24/40頁
文件大?。?/td> 0K
描述: IC DDS 1GSPS DAC 14BIT 64LFCSP
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝: 750
分辨率(位): 14 b
主 fclk: 1GHz
調(diào)節(jié)字寬(位): 48 b
電源電壓: 1.8V, 3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 帶卷 (TR)
AD9912
Rev. F | Page 30 of 40
0
676
3-
048
CSB
SCLK
SDIO
tHIGH
tLOW
tCLK
tS
tDS
tDH
tH
BIT N
BIT N + 1
Figure 56. Serial Control Port Timing—Write
Table 11. Definitions of Terms Used in Serial Control Port Timing Diagrams
Parameter
Description
tCLK
Period of SCLK
tDV
Read data valid time (time from falling edge of SCLK to valid data on SDIO/SDO)
tDS
Setup time between data and rising edge of SCLK
tDH
Hold time between data and rising edge of SCLK
tS
Setup time between CSB and SCLK
tH
Hold time between CSB and SCLK
tHI
Minimum period that SCLK should be in a logic high state
tLO
Minimum period that SCLK should be in a logic low state
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