參數(shù)資料
型號(hào)： AD9912ABCPZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 29/40頁(yè)
文件大小： 0K
描述： IC DDS 1GSPS DAC 14BIT 64LFCSP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝： 750
分辨率（位）： 14 b
主 fclk： 1GHz
調(diào)節(jié)字寬（位）： 48 b
電源電壓： 1.8V, 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
AD9912
Rev. F | Page 35 of 40
CMOS OUTPUT DIVIDER (S-DIVIDER) (REGISTER 0x0100 TO REGISTER 0x0106)
Register 0x0100 to Register 0x0103—Reserved
Register 0x0104—S-Divider
Table 21.
Bits
Bit Name
Description
[7:0]
S-divider
CMOS output divider. Divide ratio = 1 65,536. If the desired S-divider setting is greater than 65,536,
or if the signal on FDBK_IN is greater than 400 MHz, then Bit 0 in Register 0x0106 must be set. Note that
the actual S-divider is the value in this register plus 1; so to have an S-divider of 1, Register 0x0104 and
Register 0x0105 must both be 0x00. Register 0x0104 is the least significant byte.
Register 0x0105—S-Divider (Continued)
Table 22.
Bits
Bit Name
Description
[15:8]
S-divider
CMOS output divider. Divide ratio = 1 65,536. If the desired S-divider setting is greater than 65,536,
or if the signal on FDBK_IN is greater than 400 MHz, then Bit 0 in Register 0x0106 must be set. Note that
the actual S-divider is the value in this register plus 1; so to have an S-divider of 1, Register 0x0104 and
Register 0x0105 must both be 0x00. Register 0x104 is the least significant byte.
Register 0x0106—S-Divider (Continued)
Table 23.
Bits
Bit Name
Description
7
Falling edge triggered
Setting this bit inverts the reference clock before S-divider.
[6:1]
Reserved
Reserved.
0
S-divider/2
Setting this bit enables an additional /2 prescaler. See the CMOS Output Divider (S-Divider) section.
If the desired S-divider setting is greater than 65,536, or if the signal on FDBK_IN is greater than 400 MHz,
this bit must be set.
FREQUENCY TUNING WORD (REGISTER 0x01A0 TO REGISTER 0x01AD)
Register 0x01A0 to Register 0x01A5—Reserved
Register 0x01A6—FTW0 (Frequency Tuning Word)
Table 24.
Bits
Bit Name
Description
[7:0]
FTW0
These registers contain the FTW (frequency tuning word) for the DDS. The FTW determines the ratio
of the AD9912 output frequency to its DAC system clock. Register 0x01A6 is the least significant byte
of the FTW. Note that the power-up default is defined by start-up Pin S1 to Pin S4. Updates to the FTW
results in an instantaneous frequency jump but no phase discontinuity.
Register 0x01A7—FTW0 (Frequency Tuning Word) (Continued)
Table 25.
Bits
Bit Name
Description
[15:8]
FTW0
These registers contain the FTW (frequency tuning word) for the DDS. The FTW determines the ratio
of the AD9912 output frequency to its DAC system clock. Register 0x01A6 is the least significant byte
of the FTW. Note that the power-up default is defined by start-up Pin S1 to Pin S4. Updates to the FTW
results in an instantaneous frequency jump but no phase discontinuity.
Register 0x01A8—FTW0 (Frequency Tuning Word) (Continued)
Table 26.
Bits
Bit Name
Description
[23:16]
FTW0
These registers contain the FTW (frequency tuning word) for the DDS. The FTW determines the ratio
of the AD9912 output frequency to its DAC system clock. Register 0x01A6 is the least significant byte
of the FTW. Note that the power-up default is defined by start-up Pin S1 to Pin S4. Updates to the FTW
results in an instantaneous frequency jump but no phase discontinuity.
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