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參數(shù)資料
| 型號： | AD9879BSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR FRONT END 100MQFP |
| 標準包裝： | 1 |
| 位數(shù)： | 12 |
| 通道數(shù)： | 5 |
| 功率（瓦特）： | 587mW |
| 電壓 - 電源，模擬： | 3.3V |
| 電壓 - 電源，數(shù)字： | 3.3V |
| 封裝/外殼： | 100-BQFP |
| 供應商設備封裝： | 100-MQFP（14x20） |
| 包裝： | 托盤 |
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AD9879
Rev. A | Page 13 of 32
An internal PLL generates the DAC sampling frequency, fSYSCLK,
by multiplying OSCIN frequency M times. The MCLK signal
(Pin 23), fMCLK, is derived by dividing fSYSCLK by 4.
fSYSCLK = fOSCIN × M
(4)
fMCLK = fOSCIN × M/4
(5)
An external PLL loop filter (Pin 57) consisting of a series
resistor and ceramic capacitor (Figure 18, R1 = 1.3 k,
C12 = 0.01 F) is required for stability of the PLL. Also, a shield
surrounding these components is recommended to minimize
external noise coupling into the PLL’s voltage controlled
oscillator input (guard trace connected to AVDDPLL).
Figure 3 shows that ADCs are either sampled directly by a low
jitter clock at OSCIN or by a clock that is derived from the PLL
output. Operating modes can be selected in Register 0x08.
Sampling the ADCs directly with the OSCIN clock requires
MCLK to be programmed to be twice the OSCIN frequency.
PROGRAMMABLE CLOCK OUTPUT REFCLK
The AD9879 provides an auxiliary output clock on Pin 71,
REFCLK. The value of the MCLK divider bit field, R,
determines its output frequency as shown:
fREFCLK = fMCLK/R, for R = 2 3
(6)
fREFCLK = fOSCIN/R, for R = 0
(7)
In its default setting (0x00 in Register 0x01), the REFCLK pin
provides a buffered output of fOSCIN.
31
TXIQ
(1)
32
TXIQ
(0)
33
DVDD
34
DGND
35
DNC
36
PROFILE
37
RESET
38
DVDD
39
DGND
40
DGND
41
SCLK
42
CS
43
SDIO
44
SDO
2
DRGND
3
DRVDD
4
(MSB) IF(11)
7
IF(8)
6
IF(9)
5
IF(10)
1
DNC
8
IF(7)
9
IF(6)
10
IF(5)
12
IF(3)
13
IF(2)
14
IF(1)
15
IF(0)
16
(MSB) RXIQ(3)
17
RXIQ(2)
18
RXIQ(1)
19
RXIQ(0)
20
RXSYNC
21
DRGND
22
DRVDD
23
MCLK
24
DVDD
25
DGND
26
TXSYNC
27
(MSB) TXIQ(5)
28
TXIQ(4)
29
TXIQ(3)
30
TXIQ(2)
11
IF(4)
79
I+
78
I–
77
DNC
74
AGNDIQ
75
DNC
76
DNC
80
DNC
73
AVDDIQ
72
DRVDD
71
REFCLK
69
DGND
Σ-
68
Σ-
_OUT
67
FLAG1
66
DVDD
Σ-
65
CA_EN
64
CA_DATA
63
CA_CLK
62
DVDDOSC
61
OSCIN
60
XTAL
59
DGNDOSC
58
AGNDPLL
57
PLLFILT
56
AVDDPLL
55
DVDDPLL
54
DGNDPLL
53
AVDDTX
52
TX+
51
TX–
70
DRGND
45
DGNDTX
46
DVDDTX
47
PWRDN
48
REFIO
49
FSADJ
50
AGNDTX
VIDEO
IN
AGND
IF12+
IF12
–
AGND
AVDD
REFT12
REFB1
2
AVDD
AGND
IF10+
IF10
–
AGND
AVDD
REFT10
REFB1
0
AVDD
AGND
Q+
Q–
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
PIN 1
AD9879
TOP VIEW
(Pins Down)
C3
0.1
F
C1
0.1
F
CP1
10
F
C2
0.1
F
C6
0.1
F
C4
0.1
F
CP2
10
F
C5
0.1
F
C10
20pF
C11
20pF
GUARD TRACE
C12
0.01
F
R1
1.3k
C13
0.1
F
RSET
4.02k
02773-004
Figure 4. Basic Connection Diagram
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