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參數(shù)資料
| 型號： | AD9879BSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/32頁 |
| 文件大小： | 0K |
| 描述： | IC PROCESSOR FRONT END 100MQFP |
| 標準包裝： | 1 |
| 位數(shù)： | 12 |
| 通道數(shù)： | 5 |
| 功率（瓦特）： | 587mW |
| 電壓 - 電源，模擬： | 3.3V |
| 電壓 - 電源，數(shù)字： | 3.3V |
| 封裝/外殼： | 100-BQFP |
| 供應(yīng)商設(shè)備封裝： | 100-MQFP（14x20） |
| 包裝： | 托盤 |
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AD9879
Rev. A | Page 27 of 32
RECEIVE PATH (Rx)
IF10 AND IF12 ADC OPERATION
The IF10 and IF12 ADCs have a common architecture and
share many of the same characteristics from an applications
standpoint. Most of the information in this section is applicable
to both IF ADCs. Differences, where they exist, are highlighted.
INPUT SIGNAL RANGE AND DIGITAL OUTPUT
CODES
The IF ADCs have differential analog inputs labeled IF+ and
IF. The signal input, VAIN, is the voltage difference between the
two input pins, VAIN = VIF+ – VIF. The full-scale input voltage
range is determined by the internal reference voltages, REFT
and REFB, which define the top and bottom of the scale. The
peak input voltage to the ADC is the difference between REFT
and REFB, which is 1 Vppd. This results in the ADC full-scale
input voltage range of 2 Vppd. The digital output code is
straight binary and is illustrated in Table 12.
Table 12. Digital Output Codes
IF[11:0]
Input Signal Voltage
111...111
VAIN ≥ +1.0 V
111...111
VAIN = +1.0 – 1 LSB V
111...110
VAIN = +1.0 – 2 LSB V
...
100...001
VAIN = +1 LSB V
100...000
VAIN = 0.0 V
011...111
VAIN = 1 LSB V
...
000...001
VAIN = 1.0 + 2 LSB V
000...000
VAIN = 1.0 V
000...000
VAIN < 1.0 V
The IF10 ADC digital output code occupies the 10 MSBs of the
Rx digital output port (IF[11:2]). The output codes clamp to the
top or the bottom of the scale when the inputs are overdriven.
DRIVING THE INPUTS
The IF ADCs have differential switched capacitor sample-and-
hold amplifier (SHA) inputs. The nominal differential input
impedance is 4.0 k||3 pF. This impedance can be used as the
effective termination impedance when calculating filter transfer
characteristics and voltage signal attenuation from non-zero
source impedances. It should be noted, however, that for best
performance, additional requirements must be met by the
signal source. The SHA has input capacitors that must be
recharged each time the input is sampled. This results in a
dynamic input current at the device input. This demands that
the source has low (<50 V) output impedance at frequencies up
to the ADC sampling frequency. Also, the source must have
settling to better than 0.1% in <1/2 ADC CLK period.
Another consideration for getting the best performance from
the ADC inputs is the dc biasing of the input signal. Ideally, the
signal should be biased to a dc level equal to the midpoint of the
ADC reference voltages, REFT12 and REFB12. Nominally, this
level is 1.2 V. When ac-coupled, the ADC inputs self bias to this
voltage and require no additional input circuitry.
Figure 23 illustrates a recommended circuit that eases the
burden on the signal source by isolating its output from the
ADC input. The 33 series termination resistors isolate the
amplifier outputs from any capacitive load, which typically
improves settling time. The series capacitors provide ac signal
coupling which ensures the ADC inputs operate at the optimal
dc bias voltage. The shunt capacitor sources the dynamic
currents required to charge the SHA input capacitors, removing
this requirement from the ADC buffer. The values of CC and
CS should be calculated to get the correct HPF and LPF corner
frequencies.
tEE
tMD
tOD
MCLK
RXSYNC
RXIQ
DATA
I[7:4]
I[3:0]
I[7:4]
I[3:0]
Q[7:4]
Q[3:0]
IF10
IF12
IF10
IF12
IF10
IF12
REFCLK
IF DATA
M = 8
02773-021
Figure 21. Rx Port Timing (Default Mode: Multiplexed IF ADC Data)
tEE
tMD
tOD
MCLK
RXSYNC
RXIQ
DATA
I[7:4]
I[3:0]
I[7:4]
I[3:0]
Q[7:4]
Q[3:0]
IF10 OR IF12
REFCLK
IF DATA
IF10 OR IF12
M = 8
02773-022
Figure 22. Rx Port Timing (Nonmultiplexed Data)
AINP
AINN
33
CS
33
VS
02773-023
CC
Figure 23. Simple ADC Drive Configuration
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