參數(shù)資料
型號(hào)： AD9557BCPZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 81/92頁(yè)
文件大?。?/td> 0K
描述： IC CLK XLATR PLL 1250MHZ 40LFCSP
產(chǎn)品變化通告： Minor Mask Change 11/Apr/2012
標(biāo)準(zhǔn)包裝： 750
類型： 時(shí)鐘/頻率轉(zhuǎn)換器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，HSTL，LVDS
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.25GHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 40-LFCSP-VQ（6x6）
包裝： 帶卷 (TR)
AD9557
Data Sheet
Rev. B | Page 82 of 92
QUICK IN/OUT FREQUENCY SOFT PIN CONFIGURATION (REGISTER 0x0C00 TO REGISTER 0x0C08)
Table 97. Soft Pin Program Setting
Address
Bits
Bit Name
Description
0x0C00
[7:1]
Reserved
0
Enable Soft Pin
Section 1
0 (default) = disables the function of soft pin registers in Soft Pin Section 1 (Register 0x0C01 and
Register 0x0C02).
1 = enables the function of soft pin registers in Soft Pin Section 1 (Register 0x0C01 and Register
0x0C02) when the PINCONTROL pin is low at startup and/or reset.
The register in Soft Pin Section 1 configures the part into one of 256 preconfigured input-to-
output frequency translations stored in the on-chip ROM.
The registers in Soft Pin Section 1 (Register 0x0C00 to Register 0x0C02) are ignored when the
PINCONTROL pin is high at power-up and/or reset (which means the hard pin program is enabled).
0x0C01
[7:4]
Output frequency
selection
Selects one of 16 predefined output frequencies as ouptut frequency of the desired frequency
translation and reprogram the free run TW, N2, RF div, and M0 to M3 divider with the value
stored in the ROM.
[3:0]
Input frequency
selection
Selects one of 16 predefined input frequencies as the input frequency of the desired frequency
translation and reprogram the reference period, R divider, N1, FRAC1, and MOD1 in four REF
profiles with the value stored in the ROM.
0x0C02
[7:2]
Reserved
Reserved.
[1:0]
System clock PLL
ref selection
Selects one of the four predefined system PLL references for the desired frequency translation
and reprogram the system PLL configuration with the value stored in the ROM. To load values
from ROM, user must write Register 0x0C07[0] = 1 after writing this value.
System
PLL Ref
Register 0x0C02[1:0]
Equivalent System Clock PLL Settings,
Register 0x0100 to Register 0x101[3:0]
Bit 1
Bit 0
12 Bits
1
0
24.576 MHz XTAL, ×2 on, N = 16
2
0
1
49.152 MHz XTAL, ×2 on, N = 8
3
1
0
24.576 MHz XO, ×2 off, N = 32
4
1
49.152 MHz XO, ×2 off, N = 16
0x0C03
[7:1]
Reserved
Reserved.
0
Enable Soft Pin
Section 2
0 (default) = disables the function of soft pin registers in Soft Pin Section 2 (Register 0x0C04 to
Register 0x0C06).
1 = enables the function of soft pin registers in Soft Pin Section 2 (Register 0x0C04 to Register 0x0C06)
when PINCONTROL pin is low.
0x0C04
[7:4]
Reserved
Reserved.
[3:2]
REFB frequency scale
Scales selected input frequency (defined by Register 0x0C01[3:0]) for REFB.
00 (default) = divide-by-1.
01 = divide-by-4.
10 = divide-by-8.
11 = divide-by-16.
For example, if the selected input frequency is 622.08 MHz and Register 0x0C04[3:2] = 11b,
the new input frequency should be 622.08 MHz/16 = 38.8 MHz
[1:0]
REFA frequency scale
Scales selected input frequency (defined by Register 0x0C01[3:0]) for REFA.
00 (default) = divide-by-1.
01 = divide-by-4.
10 = divide-by-8.
11 = divide-by-16.
0x0C05
[7:4]
Reserved
Reserved.
[3:2]
Channel 1 output
frequency scale
Scales selected output frequency (defined by Register 0x0C01[7:4]) for Channel Divider 1 output.
00 (default) = divide-by-1.
01 = divide-by-4.
10 = divide-by-8.
11 = divide-by-16.
[1:0]
Channel 0 output
frequency scale
Scales selected output frequency (defined by Register 0x0C01[7:4]) for Channel Divider 0 output.
00 (default) = divide-by-1.
01 = divide-by-4.
10 = divide-by-8.
11 = divide-by-16.
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