參數(shù)資料
型號(hào)： AD9557BCPZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 80/92頁
文件大?。?/td> 0K
描述： IC CLK XLATR PLL 1250MHZ 40LFCSP
產(chǎn)品變化通告： Minor Mask Change 11/Apr/2012
標(biāo)準(zhǔn)包裝： 750
類型： 時(shí)鐘/頻率轉(zhuǎn)換器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，HSTL，LVDS
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.25GHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 40-LFCSP-VQ（6x6）
包裝： 帶卷 (TR)
Data Sheet
AD9557
Rev. B | Page 81 of 92
Table 93. IRQ Clearing for History Update, Frequency Limit, and Phase Slew Limit
Address
Bits
Bit Name
Description
0x0A07
[7:5]
Reserved
4
History updated
Clears history updated IRQ
3
Frequency unclamped
Clears frequency unclamped IRQ
2
Frequency clamped
Clears frequency clamped IRQ
1
Phase slew unlimited
Clears phase slew unlimited IRQ
0
Phase slew limited
Clears phase slew limited IRQ
Table 94. IRQ Clearing for Reference Inputs
Address
Bits
Bit Name
Description
0x0A08
7
Reserved
6
REFB validated
Clears REFB validated IRQ
5
REFB fault cleared
Clears REFB fault cleared IRQ
4
REFB fault
Clears REFB fault IRQ
3
Reserved
2
REFA validated
Clears REFA validated IRQ
1
REFA fault cleared
Clears REFA fault cleared IRQ
0
REFA fault
Clears REFA fault IRQ
0x0A09
[7:0]
Reserved
Incremental Phase Offset Control and Manual Reference Validation (Register 0x0A0A to Register 0x0A0D)
Table 95. Incremental Phase Offset Control
Address
Bits
Bit Name
Description
0x0A0A
[7:3]
Reserved
2
Reset phase offset
Resets the incremental phase offset to zero.
This is an autoclearing bit.
1
Decrement phase
offset
Decrements the incremental phase offset by the amount specified in the Incremental phase
lock offset step size register (Register 0x0312 to Register 0x0313).
This is an autoclearing bit.
0
Increment phase
offset
Increments the incremental phase offset by the amount specified in the Incremental phase
lock offset step size register (Register 0x0312 to Register 0x0313).
This is an autoclearing bit.
Table 96. Manual Reference Validation
Address
Bits
Bit Name
Description
0x0A0B
[7:2]
Reserved
Reserved.
1
Force Timeout B
Setting this autoclearing bit emulates timeout of the validation timer for Reference B and allows
the user to make REFB valid immediately.
0
Force Timeout A
Setting this autoclearing bit emulates timeout of the validation timer for Reference A and allows
the user to make REFA valid immediately.
0x0A0C
[7:2]
Reserved
Reserved.
1
Ref Mon Override B
Overrides the reference monitor REF FAULT signal for Reference B. Setting this bit forces REFB to be
invalid and is a useful way to force a reference switch away from REFB (default: 0b).
0
Ref Mon Override A
Overrides the reference monitor REF FAULT signal for Reference A. Setting this bit forces REFA to be
invalid and is a useful way to force a reference switch away from REFA (default: 0).
0x0A0D
[7:2]
Reserved
Reserved.
1
Ref Mon Bypass B
Setting this bit bypasses the reference monitor for Reference B and starts the REFB validation timer.
By first setting this bit, and then setting the Force Timeout B bit, REFB is valid for use by the DPLL.
However, the user should not set this bit at exactly the same time as the force timeout bit
(default: 0).
0
Ref Mon Bypass A
Setting this bit bypasses the reference monitor for Reference A and starts the REFA validation timer.
By first setting this bit, and then setting the Force Timeout B bit, REFA is valid for use by the DPLL.
However, the user should not set this bit at exactly the same time as the force timeout bit
(default: 0).
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