參數(shù)資料
型號(hào)： AD9557BCPZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 35/92頁(yè)
文件大?。?/td> 0K
描述： IC CLK XLATR PLL 1250MHZ 40LFCSP
產(chǎn)品變化通告： Minor Mask Change 11/Apr/2012
標(biāo)準(zhǔn)包裝： 750
類型： 時(shí)鐘/頻率轉(zhuǎn)換器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，HSTL，LVDS
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.25GHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 40-LFCSP-VQ（6x6）
包裝： 帶卷 (TR)
AD9557
Data Sheet
Rev. B | Page 40 of 92
A pause instruction, like an end instruction, is stored at the end
of a sequence of instructions in the scratch pad. When the
controller encounters a pause instruction during an upload
sequence, it keeps the EEPROM address pointer at its last value.
This way the user can store a new instruction sequence in the
scratch pad and upload the new sequence to the EEPROM. The
new sequence is stored in the EEPROM address locations
immediately following the previously saved sequence. This
process is repeatable until an upload sequence contains an end
instruction. The pause instruction is also useful when used in
conjunction with condition processing. It allows the EEPROM
to contain multiple occurrences of the same registers, with each
occurrence linked to a set of conditions (see the EEPROM
EEPROM Upload
To upload data to the EEPROM, the user must first ensure that
the write enable bit (Register 0x0E00, Bit 0) is set. Then, on
setting the autoclearing save to EEPROM bit (Register 0x0E02,
Bit 0), the controller initiates the EEPROM data storage process.
Uploading EEPROM data requires that the user first write an
instruction sequence into the scratch pad registers. During the
upload process, the controller reads the scratch pad data byte-
by-byte, starting at Register 0x0E10 and incrementing the
scratch pad address pointer, as it goes, until it reaches a pause or
end instruction.
As the controller reads the scratch pad data, it transfers the data
from the scratch pad to the EEPROM (byte-by-byte) and
increments the EEPROM address pointer accordingly, unless it
encounters a data instruction. A data instruction tells the
controller to transfer data from the device settings portion of
the register map to the EEPROM. The number of bytes to
transfer is encoded within the data instruction, and the starting
address for the transfer appears in the next two bytes in the
scratch pad.
When the controller encounters a data instruction, it stores the
instruction in the EEPROM, increments the EEPROM address
pointer, decodes the number of bytes to be transferred, and
increments the scratch pad address pointer. Then it retrieves the
next two bytes from the scratch pad (the target address) and
increments the scratch pad address pointer by 2. Next, the
controller transfers the specified number of bytes from the
register map (beginning at the target address) to the EEPROM.
When it completes the data transfer, the controller stores an
extra byte in the EEPROM to serve as a checksum for the
transferred block of data. To account for the checksum byte, the
controller increments the EEPROM address pointer by one
more than the number of bytes transferred. Note that, when the
controller transfers data associated with an active register, it
actually transfers the buffered contents of the register (see the
Buffered/Active Registers section for details on the difference
between buffered and active registers). This allows for the transfer
of nonzero autoclearing register contents.
Note that conditional processing (see the EEPROM Conditional
Processing section) does not occur during an upload sequence.
EEPROM Download
An EEPROM download results in data transfer from the
EEPROM to the device register map. To download data,
the user sets the autoclearing load from the EEPROM bit
(Register 0x0E03, Bit 1). This commands the controller to
initiate the EEPROM download process. During download, the
controller reads the EEPROM data byte-by-byte, incrementing
the EEPROM address pointer as it goes, until it reaches an end
instruction. As the controller reads the EEPROM data, it
executes the stored instructions, which includes transferring
stored data to the device settings portion of the register map
whenever it encounters a data instruction.
Note that conditional processing (see the EEPROM Conditional
Processing section) is applicable only when downloading.
Automatic EEPROM Download
Following a power-up, an assertion of the RESET pin, or a soft
reset (Register 0x0000, Bit 5 = 1), if the PINCONTROL pin is
low, and M3 and M2 are either high or low (see Table 22), the
instruction sequence stored in the EEPROM executes automatically
with one of eight conditions. If M3 and M2 are left floating and
the PINCONTROL pin is low, the EEPROM is bypassed and
the factory defaults are used. In this way, a previously stored set
of register values downloads automatically on power-up or with
a hard or soft reset. See the EEPROM Conditional Processing
section for details regarding conditional processing and the way
it modifies the download process.
Table 22. EEPROM Setup
M3
M2
ID
EEPROM Download?
Low
1
Yes, EEPROM Condition 1
Low
Open
2
Yes, EEPROM Condition 2
Low
High
3
Yes, EEPROM Condition 3
Open
Low
4
Yes, EEPROM Condition 4
Open
0
No
Open
High
5
Yes, EEPROM Condition 5
High
Low
6
Yes, EEPROM Condition 6
High
Open
7
Yes, EEPROM Condition 7
High
8
Yes, EEPROM Condition 8
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