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參數(shù)資料
型號(hào): AD9549ABCPZ-REEL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 71/76頁(yè)
文件大小: 0K
描述: IC CLOCK GEN/SYNCHRONIZR 64LFCSP
產(chǎn)品變化通告: AD9549A Mask Change 22/Oct/2010
標(biāo)準(zhǔn)包裝: 750
類型: 時(shí)鐘/頻率發(fā)生器,同步器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum
輸入: CMOS,LVDS,LVPECL
輸出: CMOS,HSTL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 750MHz
電源電壓: 1.71 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 帶卷 (TR)
AD9549
Rev. D | Page 73 of 76
APPLICATIONS INFORMATION
SAMPLE APPLICATIONS CIRCUIT
CLK
CLKB
SYNCB
LOW-PASS
FILTER
AD9514
/1...../32
Δt
OUT0/
OUT0B
OUT1/
OUT1B
OUT2/
OUT2B
SYSCLK
INPUT A
INPUT B
06744-
059
AD9549
DDS/
DAC
REF A
REF B
DIFF HSTL OUTPUT
FDBK_IN
FDBK_INB
CMOS OUTPUT
LDDS/CMOS
LVPECL
Figure 59. AD9549 and AD9514 Precision Clock Distribution Circuit
Applications Circuit Features
Features of this applications circuit include the following:
Input frequencies down to 8 kHz; output frequencies up to
400 MHz
Programmable loop bandwidth down to <1 Hz
Automatic redundant clock switchover with user-selectable
rate-of-phase adjustment
Automatic Stratum 3/3E clock holdover, depending on the
configuration
Phase noise (fC = 122.3 MHz and 100 Hz loop bandwidth);
100 Hz offset: 107 dBc/Hz; 1 kHz offset: 142 dBc/Hz;
100 kHz offset: 157 dBc/Hz; two zero-delay outputs with
programmable postdivider and synchronization
Two additional outputs (nonzero delay) on the AD9549
Programmable skew adjustment on one AD9514 output
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