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參數(shù)資料
| 型號： | AD9549ABCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 35/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| 產(chǎn)品變化通告： | AD9549A Mask Change 22/Oct/2010 |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 類型： | 時鐘/頻率發(fā)生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，HSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 750MHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
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AD9549
Rev. D | Page 40 of 76
The DDS output frequency listed in Table 8 assumes that
the internal DAC sampling frequency (fS) is 1 GHz. These
frequencies scale 1:1 with fS, meaning that other startup
frequencies are available by varying the SYSCLK frequency.
At startup, the internal frequency multiplier defaults to 40×
when the Xtal/PLL mode is selected via the status pins.
Note that when using this mode, the digital PLL loop is still open,
and the AD9549 is acting as a frequency synthesizer. The
frequency dividers and DPLL loop filter must still be
programmed before closing the loop.
Table 8. Default Power-Up Frequency Options for 1 GHz
System Clock
Status Pin
SYSCLK
Input Mode
Output Frequency
(MHz)
S4
S3
S2
S1
0
Xtal/PLL
0
1
Xtal /PLL
38.87939
0
1
0
Xtal /PLL
51.83411
0
1
Xtal /PLL
61.43188
0
1
0
Xtal /PLL
77.75879
0
1
0
1
Xtal /PLL
92.14783
0
1
0
Xtal /PLL
122.87903
0
1
Xtal /PLL
155.51758
1
0
Direct
0
1
0
1
Direct
38.87939
1
0
1
0
Direct
51.83411
1
0
1
Direct
61.43188
1
0
Direct
77.75879
1
0
1
Direct
92.14783
1
0
Direct
122.87903
1
Direct
155.51758
Interrupt Request (IRQ)
Any one of the four status pins (S1 to S4) can be programmed as
an IRQ pin. If a status pin is programmed as an IRQ pin, the state
of the internal IRQ flag appears on that pin. An IRQ flag is
internally generated based on the change of state of any one of
the internal status flags. The individual status flags are routed to
a read-only I/O register (status register) so that the user can
interrogate the status of any of these flags at any time. Furthermore,
each status flag is monitored for a change in state. In some cases,
only a change of state in one direction is necessary (for example, the
frequency estimate done flag), but in most cases, the status flags are
monitored for a change of state in either direction (see Figure 50).
Whether or not a particular state change is allowed to generate
an IRQ is dependent on the state of the bits in the IRQ mask
register. The user programs the mask to enable those events,
which are to constitute cause for an IRQ. If an unmasked event
occurs, it triggers the IRQ latch and the IRQ flag is asserted
(active high). The state of the IRQ flag is made available
externally via one of the programmable status pins (see the
Status Pins section).
The automatic assertion of the IRQ flag causes the contents of the
status register to be transferred to the IRQ status register. The
user can then read the IRQ status register any time after the
indication of an IRQ event (that is, assertion of the IRQ flag). By
noting the bit that is set in the IRQ register, the cause of the IRQ
event can be determined.
Once the IRQ register has been read, the user must set the IRQ
reset bit in the appropriate control register via the serial I/O port.
This restores the IRQ flag to its default state, clears the IRQ status
register, and resets the edge detection logic that monitors the
status flags in preparation for the next state change.
06744-
050
20
Q
D
IRQ
REG.
0
IRQ
EDGE
DETECT
EDGE
DETECT
EDGE
DETECT
EDGE
DETECT
EDGE
DETECT
EDGE
DETECT
EDGE
DETECT
EDGE
DETECT
EDGE
DETECT
EDGE
DETECT
EDGE
DETECT
NEW REF
FREQ. EST. DONE
ENTER HOLDOVER
EXIT HOLDOVER
PHASE LOCKED
PHASE UNLOCKED
FREQ. LOCKED
FREQ. UNLOCKED
REFA LOR
REFB LOR
REFA OOL
REFB OOL
REFA VALID
REFA INVALID
REFB VALID
REFB INVALID
STATUS REGISTER
STATUS
FLAGS
REF SELECTED (A/B)
FREQUENCY EST. DONE
HOLDOVER
PHASE LOCK
FREQUENCY LOCK
REFA LOR
REFB LOR
REFA OOL
REFB OOL
REFA VALID
REFB VALID
RS
T
IRQ RESET
11
IRQ MASK REGISTER
S
Figure 50. Interrupt Request Logic
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