參數(shù)資料
型號： AD9549ABCPZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 52/76頁
文件大小： 0K
描述： IC CLOCK GEN/SYNCHRONIZR 64LFCSP
產(chǎn)品變化通告： AD9549A Mask Change 22/Oct/2010
標(biāo)準(zhǔn)包裝： 750
類型： 時鐘/頻率發(fā)生器，同步器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，HSTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 750MHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
AD9549
Rev. D | Page 56 of 76
Register 0x0104—S-Divider (DPLL Feedback Divider)
Table 27.
Bits
Bit Name
Description
[7:0]
S-divider
Feedback divider. Divide ratio = 1 65,536. If the desired feedback ratio is greater than 65,536, or if
the feedback signal on FDBK_IN is greater than 400 MHz, then Bit 0 of Register 0x0106 must be set.
Note that the actual S-divider is the value in this register plus 1, so to have an R-divider of 1,
Register 0x0104 and Register 0x0105 must both be 0x00. Register 0x0104 is the least significant byte.
Register 0x0105—S-Divider (DPLL Feedback Divider) (Continued)
Table 28.
Bits
Bit Name
Description
[15:8]
S-divider
Feedback divider. Divide ratio = 1 65,536. If the desired feedback ratio is greater than 65,536, or if
the feedback signal on FDBK_IN is greater than 400 MHz, then Bit 0 of Register 0x0106 must be set.
Note that the actual S-divider is the value in this register plus 1, so to have an R-divider of 1,
Register 0x0104 and Register 0x0105 must both be 0x00. Register 0x0104 is the least significant byte.
Register 0x0106—S-Divider (DPLL Feedback Divider) (Continued)
Table 29.
Bits
Bit Name
Description
7
Falling edge triggered
Setting this bit inverts the reference clock before S-divider.
[6:1]
Reserved
Reserved.
0
S-divider/2
Setting this bit enables an additional /2 prescaler. See the Feedback Divider (Divide-by-S) section.
If the desired feedback ratio is greater than 65,536, or if the feedback signal on FDBK_IN is greater
than 400 MHz, then this bit must be set. An example of this case is when the PLL is locking to an
image of the DAC output that is above the Nyquist frequency.
Register 0x0107—P-Divider
Table 30.
Bits
Bit Name
Description
[4:0]
P-divider
Divide ratio. Controls the ratio of DAC sample rate to loop filter sample rate. See the Digital Loop
Filter section. Loop filter sample rate = DAC sample rate/2^(divide ratio[4:0]). For the default case
of 1 GHz DAC sample rate, and P-divider[4:0] of 5, the loop filter sample rate is 31.25 MHz. Note that
the DAC sample rate is the same as system clock.
Register 0x0108—Loop Coefficients
See the Digital Loop Filter Coefficients section. Note that the AD9549 evaluation software derives these values.
Table 31.
Bits
Bit Name
Description
[7:0]
Alpha-0
Linear coefficient for alpha coefficient.
Register 0x0109—Loop Coefficients (Continued)
Table 32.
Bits
Bit Name
Description
[11:8]
Alpha-0
Linear coefficient for alpha coefficient.
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